From d0e4cdc9c36466a3dbef8c9f9f509cce8f1a6c34 Mon Sep 17 00:00:00 2001 From: Giacomo Gabrielli Date: Tue, 23 Oct 2018 13:51:52 +0100 Subject: [PATCH] cpu: Add a memory access predicate This changeset introduces a new predicate to guard memory accesses. The most immediate use for this is to allow proper handling of predicated-false vector contiguous loads and predicated-false micro-ops of vector gather loads (added in separate changesets). Change-Id: Ice6894fe150faec2f2f7ab796a00c99ac843810a Signed-off-by: Giacomo Gabrielli Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17991 Tested-by: kokoro Reviewed-by: Bradley Wang Reviewed-by: Nikos Nikoleris Maintainer: Nikos Nikoleris --- src/cpu/base_dyn_inst.hh | 13 +++++++++++++ src/cpu/base_dyn_inst_impl.hh | 3 ++- src/cpu/checker/cpu.hh | 14 +++++++++++++- src/cpu/exec_context.hh | 4 +++- src/cpu/minor/exec_context.hh | 14 +++++++++++++- src/cpu/o3/lsq_unit_impl.hh | 10 ++++++++++ src/cpu/simple/exec_context.hh | 14 +++++++++++++- src/cpu/simple_thread.hh | 15 +++++++++++++++ 8 files changed, 82 insertions(+), 5 deletions(-) diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index f1c782956..4084241bd 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -135,6 +135,7 @@ class BaseDynInst : public ExecContext, public RefCounted EffAddrValid, RecordResult, Predicate, + MemAccPredicate, PredTaken, IsStrictlyOrdered, ReqMade, @@ -851,6 +852,18 @@ class BaseDynInst : public ExecContext, public RefCounted } } + bool + readMemAccPredicate() const + { + return instFlags[MemAccPredicate]; + } + + void + setMemAccPredicate(bool val) + { + instFlags[MemAccPredicate] = val; + } + /** Sets the ASID. */ void setASID(short addr_space_id) { asid = addr_space_id; } short getASID() { return asid; } diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh index d8473f7d5..6d3a3ac4e 100644 --- a/src/cpu/base_dyn_inst_impl.hh +++ b/src/cpu/base_dyn_inst_impl.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011 ARM Limited + * Copyright (c) 2011, 2018 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -103,6 +103,7 @@ BaseDynInst::initVars() instFlags.reset(); instFlags[RecordResult] = true; instFlags[Predicate] = true; + instFlags[MemAccPredicate] = true; lqIdx = -1; sqIdx = -1; diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 7582e5e59..8c3000005 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011, 2016-2017 ARM Limited + * Copyright (c) 2011, 2016-2018 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -424,6 +424,18 @@ class CheckerCPU : public BaseCPU, public ExecContext thread->setPredicate(val); } + bool + readMemAccPredicate() const override + { + return thread->readMemAccPredicate(); + } + + void + setMemAccPredicate(bool val) override + { + thread->setMemAccPredicate(val); + } + TheISA::PCState pcState() const override { return thread->pcState(); } void pcState(const TheISA::PCState &val) override diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index 5909af646..4cad9e3e1 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, 2016-2017 ARM Limited + * Copyright (c) 2014, 2016-2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -316,6 +316,8 @@ class ExecContext { virtual bool readPredicate() const = 0; virtual void setPredicate(bool val) = 0; + virtual bool readMemAccPredicate() const = 0; + virtual void setMemAccPredicate(bool val) = 0; /** @} */ diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh index 55391c3fa..b39bbac3f 100644 --- a/src/cpu/minor/exec_context.hh +++ b/src/cpu/minor/exec_context.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2014, 2016-2017 ARM Limited + * Copyright (c) 2011-2014, 2016-2018 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -319,6 +319,18 @@ class ExecContext : public ::ExecContext thread.setPredicate(val); } + bool + readMemAccPredicate() const override + { + return thread.readMemAccPredicate(); + } + + void + setMemAccPredicate(bool val) override + { + thread.setMemAccPredicate(val); + } + TheISA::PCState pcState() const override { diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 62402bf4f..9323e8634 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -542,6 +542,16 @@ LSQUnit::executeLoad(const DynInstPtr &inst) load_fault = inst->initiateAcc(); + if (!inst->readMemAccPredicate()) { + assert(load_fault == NoFault); + assert(inst->readPredicate()); + inst->setExecuted(); + inst->completeAcc(nullptr); + iewStage->instToCommit(inst); + iewStage->activityThisCycle(); + return NoFault; + } + if (inst->isTranslationDelayed() && load_fault == NoFault) return load_fault; diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index fb4ced381..be7a863c5 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2017 ARM Limited + * Copyright (c) 2014-2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -518,6 +518,18 @@ class SimpleExecContext : public ExecContext { } } + bool + readMemAccPredicate() const override + { + return thread->readMemAccPredicate(); + } + + void + setMemAccPredicate(bool val) override + { + thread->setMemAccPredicate(val); + } + /** * Invalidate a page in the DTLB and ITLB. */ diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 733047f71..8b5e49a3e 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -117,6 +117,9 @@ class SimpleThread : public ThreadState, public ThreadContext /** Did this instruction execute or is it predicated false */ bool predicate; + /** True if the memory access should be skipped for this instruction */ + bool memAccPredicate; + public: std::string name() const { @@ -576,6 +579,18 @@ class SimpleThread : public ThreadState, public ThreadContext unsigned readStCondFailures() const override { return storeCondFailures; } + bool + readMemAccPredicate() + { + return memAccPredicate; + } + + void + setMemAccPredicate(bool val) + { + memAccPredicate = val; + } + void setStCondFailures(unsigned sc_failures) override { -- 2.30.2