From d0ed732499f801dcd8346013e1d230ecfd0b2579 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 12 Dec 2018 13:00:50 +0000 Subject: [PATCH] fhdl.ir: fix port threading code. --- examples/alu_hier.py | 2 +- nmigen/fhdl/ir.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/examples/alu_hier.py b/examples/alu_hier.py index 81640b2..6f862ca 100644 --- a/examples/alu_hier.py +++ b/examples/alu_hier.py @@ -56,4 +56,4 @@ class ALU: alu = ALU(width=16) frag = alu.get_fragment(platform=None) # print(rtlil.convert(frag, ports=[alu.op, alu.a, alu.b, alu.o])) -print(verilog.convert(frag, ports=[alu.op, alu.a, alu.b, alu.o, alu.add.o, alu.sub.o])) +print(verilog.convert(frag, ports=[alu.op, alu.a, alu.b, alu.o])) diff --git a/nmigen/fhdl/ir.py b/nmigen/fhdl/ir.py index eeeace1..2af5a52 100644 --- a/nmigen/fhdl/ir.py +++ b/nmigen/fhdl/ir.py @@ -66,7 +66,7 @@ class Fragment: subfrag, sub_ins, sub_outs = subfrag.prepare(ports=self_used | ports, clock_domains=clock_domains) frag.subfragments[n] = (subfrag, name) - ins |= sub_ins - self_driven + ins -= sub_outs outs |= ports & sub_outs frag.add_ports(ins, outs) -- 2.30.2