From d0f39649c494ad5bf5dcf9b1e10609a43f58818f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 21 Mar 2020 11:08:29 +0000 Subject: [PATCH] add big/little byte-reversing --- src/soc/decoder/power_decoder.py | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py index d72a054f..32cdbd15 100644 --- a/src/soc/decoder/power_decoder.py +++ b/src/soc/decoder/power_decoder.py @@ -53,7 +53,7 @@ Top Level: """ -from nmigen import Module, Elaboratable, Signal +from nmigen import Module, Elaboratable, Signal, Cat, Mux from nmigen.cli import rtlil from soc.decoder.power_enums import (Function, Form, InternalOp, In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen, @@ -230,11 +230,34 @@ class PowerDecoder(Elaboratable): class TopPowerDecoder(PowerDecoder, DecodeFields): + """TopPowerDecoder + + top-level hierarchical decoder for POWER ISA + bigendian dynamically switches between big and little endian decoding + (reverses byte order) + """ def __init__(self, width, dec): PowerDecoder.__init__(self, width, dec) DecodeFields.__init__(self, SignalBitRange, [self.opcode_in]) self.create_specs() + self.raw_opcode_in = Signal.like(self.opcode_in, reset_less=True) + self.bigendian = Signal(reset_less=True) + + def elaborate(self, platform): + m = PowerDecoder.elaborate(self, platform) + comb = m.d.comb + raw_be = self.raw_opcode_in + l = [] + for i in range(0, self.width, 8): + l.append(raw_be[i:i+8]) + l.reverse() + raw_le = Cat(*l) + comb += self.opcode_in.eq(Mux(self.bigendian, raw_be, raw_le)) + return m + + def ports(self): + return [self.raw_opcode_in, self.bigendian] + PowerDecoder.ports(self) def create_pdecode(): -- 2.30.2