From d0f4a6e0dc1a10d4a7c22a02634212995df6edae Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 30 Sep 2020 10:30:41 +0100 Subject: [PATCH] comb on wr_index not sync --- src/soc/experiment/icache.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index 2b230fba..c866f024 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -671,7 +671,7 @@ class ICache(Elaboratable): m_in = self.m_in wr_index = Signal(TLB_SIZE) - sync += wr_index.eq(hash_ea(m_in.addr)) + comb += wr_index.eq(hash_ea(m_in.addr)) with m.If(m_in.tlbie & m_in.doall): # Clear all valid bits -- 2.30.2