From d1005d9e3618ae2c211ae2e8758a5026f90d9a0d Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 5 Jan 2022 20:32:22 -0800 Subject: [PATCH] add todos --- openpower/sv/bitmanip.mdwn | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn index cc91c1e42..dfa34536b 100644 --- a/openpower/sv/bitmanip.mdwn +++ b/openpower/sv/bitmanip.mdwn @@ -73,6 +73,8 @@ minor opcode allocation * ternlog bitops * GF +TODO: convert all instructions to use RT and not RS + | 0.5|6.10|11.15|16.20|21..25 | 26....30 |31| name | | -- | -- | --- | --- | ----- | -------- |--| ------ | | NN | RT | RA | RB | RC | mode 000 |1 | ternlog | @@ -94,6 +96,9 @@ minor opcode allocation ops (note that av avg and abs as well as vec scalar mask are included here) +TODO: convert from RA, RB, and RC to correct field names of RT, RA, and RB, and +double check that instructions didn't need 3 inputs. + | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name | | -- | -- | --- | --- | -- | ----- | -------- |--| ---- | | NN | RA | RB | | 0 | | 0000 110 |Rc| rsvd | -- 2.30.2