From d1041899c2d24d0e001f8a48035881c7d4553aa2 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Thu, 29 Aug 2019 20:15:13 +0200 Subject: [PATCH] i386.c (inline_secondary_memory_needed): Return true for moves between SSE and non-general registers and between mask... * config/i386/i386.c (inline_secondary_memory_needed): Return true for moves between SSE and non-general registers and between mask and non-general registers. (ix86_register_move_cost): Remove stalled comment. From-SVN: r275050 --- gcc/ChangeLog | 7 +++++++ gcc/config/i386/i386.c | 30 +++++++++++++----------------- 2 files changed, 20 insertions(+), 17 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e3f5d430856..f73e8be7df2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2019-08-29 Uroš Bizjak + + * config/i386/i386.c (inline_secondary_memory_needed): Return true + for moves between SSE and non-general registers and between + mask and non-general registers. + (ix86_register_move_cost): Remove stalled comment. + 2019-08-29 Richard Biener * config/i386/i386-features.c (general_scalar_chain::convert_insn): diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index d2d84eb1166..1c9c719f22a 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -18306,32 +18306,36 @@ inline_secondary_memory_needed (machine_mode mode, reg_class_t class1, if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2)) return true; - /* Between mask and general, we have moves no larger than word size. */ - if ((MASK_CLASS_P (class1) != MASK_CLASS_P (class2)) - && (GET_MODE_SIZE (mode) > UNITS_PER_WORD)) - return true; - /* ??? This is a lie. We do have moves between mmx/general, and for mmx/sse2. But by saying we need secondary memory we discourage the register allocator from using the mmx registers unless needed. */ if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)) return true; + /* Between mask and general, we have moves no larger than word size. */ + if (MASK_CLASS_P (class1) != MASK_CLASS_P (class2)) + { + if (!(INTEGER_CLASS_P (class1) || INTEGER_CLASS_P (class2)) + || GET_MODE_SIZE (mode) > UNITS_PER_WORD) + return true; + } + if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2)) { /* SSE1 doesn't have any direct moves from other classes. */ if (!TARGET_SSE2) return true; + /* Between SSE and general, we have moves no larger than word size. */ + if (!(INTEGER_CLASS_P (class1) || INTEGER_CLASS_P (class2)) + || GET_MODE_SIZE (mode) > UNITS_PER_WORD) + return true; + /* If the target says that inter-unit moves are more expensive than moving through memory, then don't generate them. */ if ((SSE_CLASS_P (class1) && !TARGET_INTER_UNIT_MOVES_FROM_VEC) || (SSE_CLASS_P (class2) && !TARGET_INTER_UNIT_MOVES_TO_VEC)) return true; - - /* Between SSE and general, we have moves no larger than word size. */ - if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) - return true; } return false; @@ -18608,15 +18612,7 @@ ix86_register_move_cost (machine_mode mode, reg_class_t class1_i, if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)) gcc_unreachable (); - /* Moves between SSE and integer units are expensive. */ if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2)) - - /* ??? By keeping returned value relatively high, we limit the number - of moves between integer and SSE registers for all targets. - Additionally, high value prevents problem with x86_modes_tieable_p(), - where integer modes in SSE registers are not tieable - because of missing QImode and HImode moves to, from or between - MMX/SSE registers. */ return (SSE_CLASS_P (class1) ? ix86_cost->hard_register.sse_to_integer : ix86_cost->hard_register.integer_to_sse); -- 2.30.2