From d1182f58945784de533ba81d4d4650cc5ec48dc0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 6 Apr 2022 12:29:03 +0100 Subject: [PATCH] only add clock-settings on ECP5 due to special SPI clock handling (Tercel QSPI) --- src/soc/bus/tercel.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/bus/tercel.py b/src/soc/bus/tercel.py index f04f356a..54ba9252 100644 --- a/src/soc/bus/tercel.py +++ b/src/soc/bus/tercel.py @@ -170,9 +170,11 @@ class Tercel(Elaboratable): pad = getattr(pins, "dq%d" % i) comb += pad.o.eq(self.dq_out[i]) comb += pad.oe.eq(self.dq_direction[i]) - comb += pad.o_clk.eq(ClockSignal()) comb += self.dq_in[i].eq(pad.i) - comb += pad.i_clk.eq(ClockSignal()) + # ECP5 needs special handling for the SPI clock, sigh. + if self.lattice_ecp5_usrmclk: + comb += pad.o_clk.eq(ClockSignal()) + comb += pad.i_clk.eq(ClockSignal()) # XXX invert handled by SPIFlashResource comb += pins.cs_n.eq(self.cs_n_out) # ECP5 needs special handling for the SPI clock, sigh. -- 2.30.2