From d13ac3b3d504224aa2449612ad181c27b8ab0ba4 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Wed, 3 Oct 2018 21:57:24 -0700 Subject: [PATCH] cpu/mor1kx: Adding verilog include directory. --- litex/soc/cores/cpu/mor1kx/core.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py index 7428211e..c53c6e5e 100644 --- a/litex/soc/cores/cpu/mor1kx/core.py +++ b/litex/soc/cores/cpu/mor1kx/core.py @@ -122,3 +122,4 @@ class MOR1KX(Module): os.path.abspath(os.path.dirname(__file__)), "verilog", "rtl", "verilog") platform.add_source_dir(vdir) + platform.add_verilog_include_path(vdir) -- 2.30.2