From d1448f3ccee506e55f20c6ffebe671056ddb5d36 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 2 Jun 2020 21:28:01 +0100 Subject: [PATCH] Revert "ok ok - for OP_BCREG put CTR in spr2 as well" This reverts commit 87810631b7ecbd34ad89b2853bbdb763fe003633. --- src/soc/decoder/power_decoder2.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 61caf556..84d5ed71 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -64,6 +64,12 @@ class DecodeA(Elaboratable): with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR comb += self.fast_out.ok.eq(1) + with m.Elif(op.internal_op == InternalOp.OP_BCREG): + xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO + xo5 = self.dec.FormXL.XO[5] # 3.0B p38 + with m.If(xo9 & ~xo5): + comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR + comb += self.fast_out.ok.eq(1) # MFSPR or MTSPR: move-from / move-to SPRs with m.If((op.internal_op == InternalOp.OP_MFSPR) | @@ -166,9 +172,6 @@ class DecodeB(Elaboratable): with m.Elif(xo5): comb += self.fast_out.data.eq(FastRegs.TAR) comb += self.fast_out.ok.eq(1) - with m.Else(): - comb += self.fast_out.data.eq(FastRegs.CTR) - comb += self.fast_out.ok.eq(1) return m -- 2.30.2