From d14f37d155a89491665626e720fb9c34a9e1933d Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 7 Dec 2020 04:19:08 -0800 Subject: [PATCH] arm: Use local src and dest reg index arrays. Change-Id: I7512c0abfaa2148b31b51fa43c3789bdca179105 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38381 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/arch/arm/isa/arminstobjparams.isa | 35 ++ src/arch/arm/isa/formats/basic.isa | 2 +- src/arch/arm/isa/formats/pred.isa | 48 +-- src/arch/arm/isa/formats/pseudo.isa | 4 +- src/arch/arm/isa/insts/aarch64.isa | 6 +- src/arch/arm/isa/insts/branch.isa | 42 +- src/arch/arm/isa/insts/branch64.isa | 58 +-- src/arch/arm/isa/insts/crypto.isa | 30 +- src/arch/arm/isa/insts/crypto64.isa | 20 +- src/arch/arm/isa/insts/data.isa | 16 +- src/arch/arm/isa/insts/data64.isa | 113 ++--- src/arch/arm/isa/insts/div.isa | 4 +- src/arch/arm/isa/insts/fp.isa | 537 ++++++++++++------------ src/arch/arm/isa/insts/fp64.isa | 155 +++---- src/arch/arm/isa/insts/m5ops.isa | 20 +- src/arch/arm/isa/insts/macromem.isa | 387 +++++++++-------- src/arch/arm/isa/insts/mem.isa | 24 +- src/arch/arm/isa/insts/misc.isa | 481 ++++++++++----------- src/arch/arm/isa/insts/misc64.isa | 54 +-- src/arch/arm/isa/insts/mult.isa | 15 +- src/arch/arm/isa/insts/neon.isa | 238 +++++------ src/arch/arm/isa/insts/neon64.isa | 149 +++---- src/arch/arm/isa/insts/neon64_mem.isa | 34 +- src/arch/arm/isa/insts/pauth.isa | 4 +- src/arch/arm/isa/insts/sve.isa | 179 ++++---- src/arch/arm/isa/insts/sve_mem.isa | 38 +- src/arch/arm/isa/main.isa | 2 + src/arch/arm/isa/templates/basic.isa | 5 + src/arch/arm/isa/templates/branch.isa | 16 + src/arch/arm/isa/templates/branch64.isa | 24 ++ src/arch/arm/isa/templates/data64.isa | 40 ++ src/arch/arm/isa/templates/macromem.isa | 73 ++++ src/arch/arm/isa/templates/mem.isa | 60 ++- src/arch/arm/isa/templates/mem64.isa | 68 ++- src/arch/arm/isa/templates/misc.isa | 83 ++++ src/arch/arm/isa/templates/misc64.isa | 30 ++ src/arch/arm/isa/templates/mult.isa | 8 + src/arch/arm/isa/templates/neon.isa | 20 + src/arch/arm/isa/templates/neon64.isa | 44 ++ src/arch/arm/isa/templates/pred.isa | 12 + src/arch/arm/isa/templates/semihost.isa | 2 + src/arch/arm/isa/templates/sve.isa | 181 ++++++++ src/arch/arm/isa/templates/sve_mem.isa | 42 ++ src/arch/arm/isa/templates/vfp.isa | 20 + src/arch/arm/isa/templates/vfp64.isa | 8 + 45 files changed, 2078 insertions(+), 1353 deletions(-) create mode 100644 src/arch/arm/isa/arminstobjparams.isa diff --git a/src/arch/arm/isa/arminstobjparams.isa b/src/arch/arm/isa/arminstobjparams.isa new file mode 100644 index 000000000..f8fab2332 --- /dev/null +++ b/src/arch/arm/isa/arminstobjparams.isa @@ -0,0 +1,35 @@ +// -*- mode:c++ -*- + +// Copyright 2021 Google Inc. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +let {{ + +class ArmInstObjParams(InstObjParams): + def __init__(self, *args, **kwargs): + super(ArmInstObjParams, self).__init__(*args, **kwargs) + self.padSrcRegIdx(self.operands.numDestRegs) + +}}; diff --git a/src/arch/arm/isa/formats/basic.isa b/src/arch/arm/isa/formats/basic.isa index 985fa6bdf..66fa99f99 100644 --- a/src/arch/arm/isa/formats/basic.isa +++ b/src/arch/arm/isa/formats/basic.isa @@ -28,7 +28,7 @@ // The most basic instruction format... def format BasicOp(code, *flags) {{ - iop = InstObjParams(name, Name, 'ArmStaticInst', code, flags) + iop = ArmInstObjParams(name, Name, 'ArmStaticInst', code, flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa index 67861efd0..689a71d34 100644 --- a/src/arch/arm/isa/formats/pred.isa +++ b/src/arch/arm/isa/formats/pred.isa @@ -141,18 +141,16 @@ def format DataOp(code, flagtype = logic) {{ immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size, shift, OptShiftRmCondCodesC); op2 = op2;''' + code - regIop = InstObjParams(name, Name, 'PredIntOp', - {"code": regCode, - "predicate_test": pickPredicate(regCode)}) - immIop = InstObjParams(name, Name + "Imm", 'PredIntOp', - {"code": immCode, - "predicate_test": pickPredicate(imm)}) - regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp', - {"code": regCode + regCcCode, - "predicate_test": pickPredicate(regCode + regCcCode)}) - immCcIop = InstObjParams(name, Name + "ImmCc", 'PredIntOp', - {"code": immCode + immCcCode, - "predicate_test": pickPredicate(immCode + immCcCode)}) + regIop = ArmInstObjParams(name, Name, 'PredIntOp', + { "code" : regCode, "predicate_test" : pickPredicate(regCode) }) + immIop = ArmInstObjParams(name, Name + "Imm", 'PredIntOp', + { "code" : immCode, "predicate_test" : pickPredicate(imm) }) + regCcIop = ArmInstObjParams(name, Name + "Cc", 'PredIntOp', + { "code" : regCode + regCcCode, + "predicate_test" : pickPredicate(regCode + regCcCode) }) + immCcIop = ArmInstObjParams(name, Name + "ImmCc", 'PredIntOp', + { "code" : immCode + immCcCode, + "predicate_test" : pickPredicate(immCode + immCcCode) }) header_output = BasicDeclare.subst(regIop) + \ BasicDeclare.subst(immIop) + \ BasicDeclare.subst(regCcIop) + \ @@ -170,12 +168,12 @@ def format DataOp(code, flagtype = logic) {{ def format DataImmOp(code, flagtype = logic) {{ code += "resTemp = resTemp;" - iop = InstObjParams(name, Name, 'PredImmOp', - {"code": code, - "predicate_test": pickPredicate(code)}) - ccIop = InstObjParams(name, Name + "Cc", 'PredImmOp', - {"code": code + getImmCcCode(flagtype), - "predicate_test": pickPredicate(code + getImmCcCode(flagtype))}) + iop = ArmInstObjParams(name, Name, 'PredImmOp', + { "code" : code, "predicate_test" : pickPredicate(code) }) + ccIop = ArmInstObjParams(name, Name + "Cc", 'PredImmOp', + { "code" : code + getImmCcCode(flagtype), + "predicate_test" : + pickPredicate(code + getImmCcCode(flagtype)) }) header_output = BasicDeclare.subst(iop) + \ BasicDeclare.subst(ccIop) decoder_output = BasicConstructor.subst(iop) + \ @@ -186,10 +184,9 @@ def format DataImmOp(code, flagtype = logic) {{ }}; def format PredOp(code, *opt_flags) {{ - iop = InstObjParams(name, Name, 'PredOp', - {"code": code, - "predicate_test": pickPredicate(code)}, - opt_flags) + iop = ArmInstObjParams(name, Name, 'PredOp', + { "code" : code, "predicate_test" : pickPredicate(code) }, + opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) @@ -197,10 +194,9 @@ def format PredOp(code, *opt_flags) {{ }}; def format PredImmOp(code, *opt_flags) {{ - iop = InstObjParams(name, Name, 'PredImmOp', - {"code": code, - "predicate_test": pickPredicate(code)}, - opt_flags) + iop = ArmInstObjParams(name, Name, 'PredImmOp', + { "code" : code, "predicate_test": pickPredicate(code) }, + opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) diff --git a/src/arch/arm/isa/formats/pseudo.isa b/src/arch/arm/isa/formats/pseudo.isa index d827aa400..a16f038ed 100644 --- a/src/arch/arm/isa/formats/pseudo.isa +++ b/src/arch/arm/isa/formats/pseudo.isa @@ -83,11 +83,11 @@ def format Unknown() {{ // def format FailUnimpl() {{ - iop = InstObjParams(name, 'FailUnimplemented') + iop = ArmInstObjParams(name, 'FailUnimplemented') decode_block = BasicDecodeWithMnemonic.subst(iop) }}; def format WarnUnimpl() {{ - iop = InstObjParams(name, 'WarnUnimplemented') + iop = ArmInstObjParams(name, 'WarnUnimplemented') decode_block = BasicDecodeWithMnemonic.subst(iop) }}; diff --git a/src/arch/arm/isa/insts/aarch64.isa b/src/arch/arm/isa/insts/aarch64.isa index 17513d05f..fbedf89f0 100644 --- a/src/arch/arm/isa/insts/aarch64.isa +++ b/src/arch/arm/isa/insts/aarch64.isa @@ -37,19 +37,19 @@ let {{ movzCode = 'Dest64 = ((uint64_t)imm1) << imm2;' - movzIop = InstObjParams("movz", "Movz", "RegImmImmOp", movzCode, []) + movzIop = ArmInstObjParams("movz", "Movz", "RegImmImmOp", movzCode, []) header_output += RegImmImmOpDeclare.subst(movzIop) decoder_output += RegImmImmOpConstructor.subst(movzIop) exec_output += BasicExecute.subst(movzIop) movkCode = 'Dest64 = insertBits(Dest64, imm2 + 15, imm2, imm1);' - movkIop = InstObjParams("movk", "Movk", "RegImmImmOp", movkCode, []) + movkIop = ArmInstObjParams("movk", "Movk", "RegImmImmOp", movkCode, []) header_output += RegImmImmOpDeclare.subst(movkIop) decoder_output += RegImmImmOpConstructor.subst(movkIop) exec_output += BasicExecute.subst(movkIop) movnCode = 'Dest64 = ~(((uint64_t)imm1) << imm2);' - movnIop = InstObjParams("movn", "Movn", "RegImmImmOp", movnCode, []) + movnIop = ArmInstObjParams("movn", "Movn", "RegImmImmOp", movnCode, []) header_output += RegImmImmOpDeclare.subst(movnIop) decoder_output += RegImmImmOpConstructor.subst(movnIop) exec_output += BasicExecute.subst(movnIop) diff --git a/src/arch/arm/isa/insts/branch.isa b/src/arch/arm/isa/insts/branch.isa index 0928e66e5..33bb1ff5f 100644 --- a/src/arch/arm/isa/insts/branch.isa +++ b/src/arch/arm/isa/insts/branch.isa @@ -58,9 +58,9 @@ let {{ instFlags += ["IsCall"] - bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond", - {"code": bCode, "predicate_test": predicateTest, - "brTgtCode" : br_tgt_code}, instFlags) + bIop = ArmInstObjParams(mnem, mnem.capitalize(), "BranchImmCond", + { "code" : bCode, "predicate_test" : predicateTest, + "brTgtCode" : br_tgt_code }, instFlags) header_output += BranchImmCondDeclare.subst(bIop) decoder_output += BranchImmCondConstructor.subst(bIop) + \ BranchTarget.subst(bIop) @@ -138,10 +138,10 @@ let {{ code = blxCode % {"link": linkStr, "newPC": newPC, "branch": branchStr} - blxIop = InstObjParams(mnem, Name, base, - {"code": code, "brTgtCode" : br_tgt_code, - "predicate_test": predicateTest, - "is_ras_pop" : isRasPop }, instFlags) + blxIop = ArmInstObjParams(mnem, Name, base, + { "code" : code, "brTgtCode" : br_tgt_code, + "predicate_test": predicateTest, + "is_ras_pop" : isRasPop }, instFlags) header_output += declare.subst(blxIop) decoder_output += constructor.subst(blxIop) exec_output += PredOpExecute.subst(blxIop) @@ -159,11 +159,11 @@ let {{ IWNPC = Op1; ''' - bxjIop = InstObjParams("bxj", "BxjReg", "BranchRegCond", - {"code": bxjcode, - "predicate_test": predicateTest, - "is_ras_pop": "op1 == INTREG_LR" }, - ["IsIndirectControl"]) + bxjIop = ArmInstObjParams("bxj", "BxjReg", "BranchRegCond", + { "code": bxjcode, + "predicate_test": predicateTest, + "is_ras_pop": "op1 == INTREG_LR" }, + ["IsIndirectControl"]) header_output += BranchRegCondDeclare.subst(bxjIop) decoder_output += BranchRegCondConstructor.subst(bxjIop) exec_output += PredOpExecute.subst(bxjIop) @@ -173,10 +173,10 @@ let {{ code = 'NPC = (uint32_t)(PC + imm);\n' br_tgt_code = '''pcs.instNPC((uint32_t)(branchPC.instPC() + imm));''' predTest = "Op1 %(test)s 0" % {"test": test} - iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg", - {"code": code, "predicate_test": predTest, - "brTgtCode" : br_tgt_code}, - ["IsDirectControl"]) + iop = ArmInstObjParams(mnem, mnem.capitalize(), "BranchImmReg", + { "code" : code, "predicate_test" : predTest, + "brTgtCode" : br_tgt_code}, + ["IsDirectControl"]) header_output += BranchImmRegDeclare.subst(iop) decoder_output += BranchImmRegConstructor.subst(iop) + \ BranchTarget.subst(iop) @@ -200,11 +200,11 @@ let {{ ''' accCode = 'NPC = PC + 2 * (Mem_ub)' mnem = "tbb" - iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg", - {'ea_code': eaCode, - 'memacc_code': accCode, - 'predicate_test': predicateTest}, - ["IsIndirectControl"]) + iop = ArmInstObjParams(mnem, mnem.capitalize(), "BranchRegReg", + { 'ea_code' : eaCode, + 'memacc_code' : accCode, + 'predicate_test' : predicateTest}, + ["IsIndirectControl"]) header_output += BranchTableDeclare.subst(iop) decoder_output += BranchRegRegConstructor.subst(iop) exec_output += LoadExecute.subst(iop) + \ diff --git a/src/arch/arm/isa/insts/branch64.isa b/src/arch/arm/isa/insts/branch64.isa index 9cbeebc28..10a352fdd 100644 --- a/src/arch/arm/isa/insts/branch64.isa +++ b/src/arch/arm/isa/insts/branch64.isa @@ -50,8 +50,8 @@ let {{ bCode += 'XLR = RawPC + 4;\n' instFlags += ['IsCall'] - bIop = InstObjParams(mnem, mnem.capitalize() + "64", - "BranchImm64", bCode, instFlags) + bIop = ArmInstObjParams(mnem, mnem.capitalize() + "64", + "BranchImm64", bCode, instFlags) header_output += BranchImm64Declare.subst(bIop) decoder_output += BranchImm64Constructor.subst(bIop) exec_output += BasicExecute.subst(bIop) @@ -65,8 +65,8 @@ let {{ bCode += 'XLR = RawPC + 4;\n' instFlags += ['IsCall'] - bIop = InstObjParams(mnem, mnem.capitalize() + "64", - "BranchReg64", bCode, instFlags) + bIop = ArmInstObjParams(mnem, mnem.capitalize() + "64", + "BranchReg64", bCode, instFlags) header_output += BranchReg64Declare.subst(bIop) decoder_output += BranchReg64Constructor.subst(bIop) exec_output += BasicExecute.subst(bIop) @@ -82,8 +82,8 @@ let {{ bCode += 'XLR = RawPC + 4;\n' instFlags += ['IsCall'] - bIop = InstObjParams(mnem, mnem.capitalize(), - "BranchRegReg64", bCode, instFlags) + bIop = ArmInstObjParams(mnem, mnem.capitalize(), + "BranchRegReg64", bCode, instFlags) header_output += BranchRegReg64Declare.subst(bIop) decoder_output += BranchRegReg64Constructor.subst(bIop) exec_output += BasicExecute.subst(bIop) @@ -101,8 +101,8 @@ let {{ bCode += 'XLR = RawPC + 4;\n' instFlags += ['IsCall'] - bIop = InstObjParams(mnem, mnem.capitalize(), - "BranchReg64", bCode, instFlags) + bIop = ArmInstObjParams(mnem, mnem.capitalize(), + "BranchReg64", bCode, instFlags) header_output += BranchReg64Declare.subst(bIop) decoder_output += BranchReg64Constructor.subst(bIop) exec_output += BasicExecute.subst(bIop) @@ -118,8 +118,8 @@ let {{ bCode += 'XLR = RawPC + 4;\n' instFlags += ['IsCall'] - bIop = InstObjParams(mnem, mnem.capitalize(), - "BranchRegReg64", bCode, instFlags) + bIop = ArmInstObjParams(mnem, mnem.capitalize(), + "BranchRegReg64", bCode, instFlags) header_output += BranchRegReg64Declare.subst(bIop) decoder_output += BranchRegReg64Constructor.subst(bIop) exec_output += BasicExecute.subst(bIop) @@ -137,8 +137,8 @@ let {{ bCode += 'XLR = RawPC + 4;\n' instFlags += ['IsCall'] - bIop = InstObjParams(mnem, mnem.capitalize(), - "BranchReg64", bCode, instFlags) + bIop = ArmInstObjParams(mnem, mnem.capitalize(), + "BranchReg64", bCode, instFlags) header_output += BranchReg64Declare.subst(bIop) decoder_output += BranchReg64Constructor.subst(bIop) exec_output += BasicExecute.subst(bIop) @@ -152,8 +152,8 @@ let {{ else NPC = NPC; ''' - bIop = InstObjParams("b", "BCond64", "BranchImmCond64", bCode, - ['IsCondControl', 'IsDirectControl']) + bIop = ArmInstObjParams("b", "BCond64", "BranchImmCond64", bCode, + ['IsCondControl', 'IsDirectControl']) header_output += BranchImmCond64Declare.subst(bIop) decoder_output += BranchImmCond64Constructor.subst(bIop) exec_output += BasicExecute.subst(bIop) @@ -163,7 +163,7 @@ let {{ 'currEL(xc->tcBase()), true);\n') instFlags = ['IsIndirectControl', 'IsUncondControl', 'IsReturn'] - bIop = InstObjParams('ret', 'Ret64', "BranchRet64", bCode, instFlags) + bIop = ArmInstObjParams('ret', 'Ret64', "BranchRet64", bCode, instFlags) header_output += BranchReg64Declare.subst(bIop) decoder_output += BranchReg64Constructor.subst(bIop) exec_output += BasicExecute.subst(bIop) @@ -175,7 +175,7 @@ let {{ bCode += (' if (fault == NoFault)\n' ' NPC = purifyTaggedAddr(XOp1, xc->tcBase(), ' 'currEL(xc->tcBase()), true);\n') - bIop = InstObjParams('retaa', 'Retaa', "BranchRetA64", bCode, instFlags) + bIop = ArmInstObjParams('retaa', 'Retaa', "BranchRetA64", bCode, instFlags) header_output += BasicDeclare.subst(bIop) decoder_output += BasicConstructor64.subst(bIop) exec_output += BasicExecute.subst(bIop) @@ -187,7 +187,7 @@ let {{ bCode += (' if (fault == NoFault)\n' ' NPC = purifyTaggedAddr(XOp1, xc->tcBase(), ' 'currEL(xc->tcBase()), true);\n') - bIop = InstObjParams('retab', 'Retab', "BranchRetA64", bCode, instFlags) + bIop = ArmInstObjParams('retab', 'Retab', "BranchRetA64", bCode, instFlags) header_output += BasicDeclare.subst(bIop) decoder_output += BasicConstructor64.subst(bIop) exec_output += BasicExecute.subst(bIop) @@ -257,8 +257,8 @@ let {{ } ''' instFlags = ['IsSerializeAfter', 'IsNonSpeculative', 'IsSquashAfter'] - bIop = InstObjParams('eret', 'Eret64', "BranchEret64", - bCode%{'op': ''}, instFlags) + bIop = ArmInstObjParams('eret', 'Eret64', "BranchEret64", + bCode%{'op': ''}, instFlags) header_output += BasicDeclare.subst(bIop) decoder_output += BasicConstructor64.subst(bIop) exec_output += BasicExecute.subst(bIop) @@ -267,8 +267,8 @@ let {{ pac_code = ''' fault = authIA(xc->tcBase(), newPc, XOp1, &newPc); ''' - bIop = InstObjParams('eretaa', 'Eretaa', "BranchEretA64", - bCode % {'op': pac_code} , instFlags) + bIop = ArmInstObjParams('eretaa', 'Eretaa', "BranchEretA64", + bCode % {'op': pac_code} , instFlags) header_output += BasicDeclare.subst(bIop) decoder_output += BasicConstructor64.subst(bIop) exec_output += BasicExecute.subst(bIop) @@ -277,8 +277,8 @@ let {{ pac_code = ''' fault = authIB(xc->tcBase(), newPc, XOp1, &newPc); ''' - bIop = InstObjParams('eretab', 'Eretab', "BranchEretA64", - bCode % {'op': pac_code} , instFlags) + bIop = ArmInstObjParams('eretab', 'Eretab', "BranchEretA64", + bCode % {'op': pac_code} , instFlags) header_output += BasicDeclare.subst(bIop) decoder_output += BasicConstructor64.subst(bIop) exec_output += BasicExecute.subst(bIop) @@ -289,9 +289,9 @@ let {{ 'purifyTaggedAddr(RawPC + imm, xc->tcBase(), ' 'currEL(xc->tcBase()), true) : NPC;\n') code = code % {"test": test} - iop = InstObjParams(mnem, mnem.capitalize() + "64", - "BranchImmReg64", code, - ['IsCondControl', 'IsDirectControl']) + iop = ArmInstObjParams(mnem, mnem.capitalize() + "64", + "BranchImmReg64", code, + ['IsCondControl', 'IsDirectControl']) header_output += BranchImmReg64Declare.subst(iop) decoder_output += BranchImmReg64Constructor.subst(iop) exec_output += BasicExecute.subst(iop) @@ -302,9 +302,9 @@ let {{ 'purifyTaggedAddr(RawPC + imm2, xc->tcBase(), ' 'currEL(xc->tcBase()), true) : NPC;\n') code = code % {"test": test} - iop = InstObjParams(mnem, mnem.capitalize() + "64", - "BranchImmImmReg64", code, - ['IsCondControl', 'IsDirectControl']) + iop = ArmInstObjParams(mnem, mnem.capitalize() + "64", + "BranchImmImmReg64", code, + ['IsCondControl', 'IsDirectControl']) header_output += BranchImmImmReg64Declare.subst(iop) decoder_output += BranchImmImmReg64Constructor.subst(iop) exec_output += BasicExecute.subst(iop) diff --git a/src/arch/arm/isa/insts/crypto.isa b/src/arch/arm/isa/insts/crypto.isa index a75cf292e..b6c3ad3c2 100644 --- a/src/arch/arm/isa/insts/crypto.isa +++ b/src/arch/arm/isa/insts/crypto.isa @@ -94,11 +94,11 @@ let {{ crypto_prefix = enable_check + cryptoRegRegRegPrefix cryptocode = crypto_prefix + crypto_func + cryptoSuffix - cryptoiop = InstObjParams(name, Name, "RegRegRegOp", - { "code": cryptocode, - "r_count": 4, - "predicate_test": predicateTest, - "op_class": opClass}, []) + cryptoiop = ArmInstObjParams(name, Name, "RegRegRegOp", + { "code": cryptocode, + "r_count": 4, + "predicate_test": predicateTest, + "op_class": opClass}, []) header_output += RegRegRegOpDeclare.subst(cryptoiop) decoder_output += RegRegRegOpConstructor.subst(cryptoiop) exec_output += CryptoPredOpExecute.subst(cryptoiop) @@ -109,11 +109,11 @@ let {{ crypto_prefix = enable_check + cryptoRegRegPrefix cryptocode = crypto_prefix + crypto_func + cryptoSuffix - cryptoiop = InstObjParams(name, Name, "RegRegOp", - { "code": cryptocode, - "r_count": 4, - "predicate_test": predicateTest, - "op_class": opClass}, []) + cryptoiop = ArmInstObjParams(name, Name, "RegRegOp", + { "code": cryptocode, + "r_count": 4, + "predicate_test": predicateTest, + "op_class": opClass}, []) header_output += RegRegOpDeclare.subst(cryptoiop) decoder_output += RegRegOpConstructor.subst(cryptoiop) exec_output += CryptoPredOpExecute.subst(cryptoiop) @@ -124,11 +124,11 @@ let {{ crypto_prefix = enable_check + cryptoRegRegPrefix cryptocode = crypto_prefix + crypto_func + cryptoSuffix - cryptoiop = InstObjParams(name, Name, "RegRegImmOp", - { "code": cryptocode, - "r_count": 4, - "predicate_test": predicateTest, - "op_class": opClass}, []) + cryptoiop = ArmInstObjParams(name, Name, "RegRegImmOp", + { "code": cryptocode, + "r_count": 4, + "predicate_test": predicateTest, + "op_class": opClass}, []) header_output += RegRegImmOpDeclare.subst(cryptoiop) decoder_output += RegRegImmOpConstructor.subst(cryptoiop) exec_output += CryptoPredOpExecute.subst(cryptoiop) diff --git a/src/arch/arm/isa/insts/crypto64.isa b/src/arch/arm/isa/insts/crypto64.isa index 4dd5fe5f5..35ea4fef6 100644 --- a/src/arch/arm/isa/insts/crypto64.isa +++ b/src/arch/arm/isa/insts/crypto64.isa @@ -92,11 +92,11 @@ let {{ crypto_prefix = enable_check + cryptoRegRegRegPrefix cryptocode = crypto_prefix + crypto_func + cryptoSuffix - cryptoiop = InstObjParams(name, Name, "RegRegRegOp", - { "code": cryptocode, - "r_count": 4, - "predicate_test": predicateTest, - "op_class": opClass}, []) + cryptoiop = ArmInstObjParams(name, Name, "RegRegRegOp", + { "code": cryptocode, + "r_count": 4, + "predicate_test": predicateTest, + "op_class": opClass}, []) header_output += RegRegRegOpDeclare.subst(cryptoiop) decoder_output += RegRegRegOpConstructor.subst(cryptoiop) exec_output += CryptoPredOpExecute.subst(cryptoiop) @@ -107,11 +107,11 @@ let {{ crypto_prefix = enable_check + cryptoRegRegPrefix cryptocode = crypto_prefix + crypto_func + cryptoSuffix - cryptoiop = InstObjParams(name, Name, "RegRegOp", - { "code": cryptocode, - "r_count": 4, - "predicate_test": predicateTest, - "op_class": opClass}, []) + cryptoiop = ArmInstObjParams(name, Name, "RegRegOp", + { "code": cryptocode, + "r_count": 4, + "predicate_test": predicateTest, + "op_class": opClass}, []) header_output += RegRegOpDeclare.subst(cryptoiop) decoder_output += RegRegOpConstructor.subst(cryptoiop) exec_output += CryptoPredOpExecute.subst(cryptoiop) diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa index 70b9c5529..d7a957d2c 100644 --- a/src/arch/arm/isa/insts/data.isa +++ b/src/arch/arm/isa/insts/data.isa @@ -130,11 +130,13 @@ let {{ secondOpRe.sub(immOp2, vCode)) immCode = secondOpRe.sub(immOp2, code) - immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp", + immIop = ArmInstObjParams(mnem, mnem.capitalize() + suffix, + "DataImmOp", {"code" : immCode, "is_branch" : isBranch, "predicate_test": pickPredicate(immCode)}, instFlags) - immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", + immIopCc = ArmInstObjParams(mnem + "s", + mnem.capitalize() + suffix + "Cc", "DataImmOp", {"code" : immCode + immCcCode, "is_branch" : isBranch, @@ -175,11 +177,13 @@ let {{ regCode = re.sub('OptShiftRmCondCodesC', 'CondCodesC', regCode) regCcCode = re.sub('OptShiftRmCondCodesC', 'CondCodesC', regCcCode) - regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp", + regIop = ArmInstObjParams(mnem, mnem.capitalize() + suffix, + "DataRegOp", {"code" : regCode, "is_ras_pop" : isRasPop, "is_branch" : isBranch, "predicate_test": pickPredicate(regCode)}, instFlags) - regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", + regIopCc = ArmInstObjParams(mnem + "s", + mnem.capitalize() + suffix + "Cc", "DataRegOp", {"code" : regCode + regCcCode, "predicate_test": pickPredicate(regCode + regCcCode), @@ -215,11 +219,11 @@ let {{ secondOpRe.sub(regRegOp2, vCode)) regRegCode = secondOpRe.sub(regRegOp2, code) - regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix, + regRegIop = ArmInstObjParams(mnem, mnem.capitalize() + suffix, "DataRegRegOp", {"code" : regRegCode, "predicate_test": pickPredicate(regRegCode)}) - regRegIopCc = InstObjParams(mnem + "s", + regRegIopCc = ArmInstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", "DataRegRegOp", {"code" : regRegCode + regRegCcCode, diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa index 6ca6aa308..1cd17b79a 100644 --- a/src/arch/arm/isa/insts/data64.isa +++ b/src/arch/arm/isa/insts/data64.isa @@ -96,8 +96,8 @@ let {{ ''' + code ccCode = createCcCode64(carryCode64[flagType], overflowCode64[flagType]) Name = mnem.capitalize() + suffix - iop = InstObjParams(mnem, Name, base, code) - iopCc = InstObjParams(mnem + "s", Name + "Cc", base, code + ccCode) + iop = ArmInstObjParams(mnem, Name, base, code) + iopCc = ArmInstObjParams(mnem + "s", Name + "Cc", base, code + ccCode) def subst(iop): global header_output, decoder_output, exec_output @@ -154,8 +154,8 @@ let {{ global header_output, decoder_output, exec_output classNamePrefix = mnem[0].upper() + mnem[1:] templateBase = "DataXImm" - iop = InstObjParams(mnem, classNamePrefix + "64", - templateBase + "Op", code, optArgs) + iop = ArmInstObjParams(mnem, classNamePrefix + "64", + templateBase + "Op", code, optArgs) header_output += eval(templateBase + "Declare").subst(iop) decoder_output += eval(templateBase + "Constructor").subst(iop) exec_output += BasicExecute.subst(iop) @@ -166,13 +166,14 @@ let {{ templateBase = "DataX%dReg" % regOps classNamePrefix = mnem[0].upper() + mnem[1:] if overrideOpClass: - iop = InstObjParams(mnem, classNamePrefix + "64", - templateBase + "Op", - { 'code': code, 'op_class': overrideOpClass}, - optArgs) + iop = ArmInstObjParams(mnem, classNamePrefix + "64", + templateBase + "Op", + { 'code': code, + 'op_class': overrideOpClass }, + optArgs) else: - iop = InstObjParams(mnem, classNamePrefix + "64", - templateBase + "Op", code, optArgs) + iop = ArmInstObjParams(mnem, classNamePrefix + "64", + templateBase + "Op", code, optArgs) header_output += eval(templateBase + "Declare").subst(iop) decoder_output += eval(templateBase + "Constructor").subst(iop) exec_output += BasicExecute.subst(iop) @@ -342,9 +343,9 @@ let {{ mrsCode = mrs_check_code + ''' XDest = MiscOp1_ud; ''' - mrsIop = InstObjParams("mrs", "Mrs64", "RegMiscRegImmOp64", - mrsCode, - ["IsSerializeBefore"]) + mrsIop = ArmInstObjParams("mrs", "Mrs64", "RegMiscRegImmOp64", + mrsCode, + ["IsSerializeBefore"]) header_output += RegMiscRegOp64Declare.subst(mrsIop) decoder_output += RegMiscRegOp64Constructor.subst(mrsIop) exec_output += BasicExecute.subst(mrsIop) @@ -360,9 +361,9 @@ let {{ msrCode = msr_check_code + ''' MiscDest_ud = XOp1; ''' - msrIop = InstObjParams("msr", "Msr64", "MiscRegRegImmOp64", - msrCode, - ["IsSerializeAfter", "IsNonSpeculative"]) + msrIop = ArmInstObjParams("msr", "Msr64", "MiscRegRegImmOp64", + msrCode, + ["IsSerializeAfter", "IsNonSpeculative"]) header_output += MiscRegRegOp64Declare.subst(msrIop) decoder_output += MiscRegRegOp64Constructor.subst(msrIop) exec_output += BasicExecute.subst(msrIop) @@ -386,13 +387,13 @@ let {{ ''' - msrDCZVAIop = InstObjParams("dc zva", "Dczva", "SysDC64", - { "ea_code" : msrdczva_ea_code, - "memacc_code" : ';', - "use_uops" : 0, - "op_wb" : ";", - "fa_code" : ";"}, - ['IsStore']); + msrDCZVAIop = ArmInstObjParams("dc zva", "Dczva", "SysDC64", + { "ea_code" : msrdczva_ea_code, + "memacc_code" : ';', + "use_uops" : 0, + "op_wb" : ";", + "fa_code" : ";"}, + ['IsStore']); header_output += DCStore64Declare.subst(msrDCZVAIop); decoder_output += DCStore64Constructor.subst(msrDCZVAIop); exec_output += DCStore64Execute.subst(msrDCZVAIop); @@ -417,13 +418,13 @@ let {{ EA &= ~(op_size - 1); ''' - msrDCCVAUIop = InstObjParams("dc cvau", "Dccvau", "SysDC64", - { "ea_code" : msrdccvau_ea_code, - "memacc_code" : ';', - "use_uops" : 0, - "op_wb" : ";", - "fa_code" : cachem_fa}, - ['IsStore']); + msrDCCVAUIop = ArmInstObjParams("dc cvau", "Dccvau", "SysDC64", + { "ea_code" : msrdccvau_ea_code, + "memacc_code" : ';', + "use_uops" : 0, + "op_wb" : ";", + "fa_code" : cachem_fa}, + ['IsStore']); header_output += DCStore64Declare.subst(msrDCCVAUIop); decoder_output += DCStore64Constructor.subst(msrDCCVAUIop); exec_output += DCStore64Execute.subst(msrDCCVAUIop); @@ -441,13 +442,13 @@ let {{ EA &= ~(op_size - 1); ''' - msrDCCVACIop = InstObjParams("dc cvac", "Dccvac", "SysDC64", - { "ea_code" : msrdccvac_ea_code, - "memacc_code" : ';', - "use_uops" : 0, - "op_wb" : ";", - "fa_code" : cachem_fa}, - ['IsStore']); + msrDCCVACIop = ArmInstObjParams("dc cvac", "Dccvac", "SysDC64", + { "ea_code" : msrdccvac_ea_code, + "memacc_code" : ';', + "use_uops" : 0, + "op_wb" : ";", + "fa_code" : cachem_fa}, + ['IsStore']); header_output += DCStore64Declare.subst(msrDCCVACIop); decoder_output += DCStore64Constructor.subst(msrDCCVACIop); exec_output += DCStore64Execute.subst(msrDCCVACIop); @@ -466,13 +467,13 @@ let {{ EA &= ~(op_size - 1); ''' - msrDCCIVACIop = InstObjParams("dc civac", "Dccivac", "SysDC64", - { "ea_code" : msrdccivac_ea_code, - "memacc_code" : ';', - "use_uops" : 0, - "op_wb" : ";", - "fa_code" : cachem_fa}, - ['IsStore']); + msrDCCIVACIop = ArmInstObjParams("dc civac", "Dccivac", "SysDC64", + { "ea_code" : msrdccivac_ea_code, + "memacc_code" : ';', + "use_uops" : 0, + "op_wb" : ";", + "fa_code" : cachem_fa}, + ['IsStore']); header_output += DCStore64Declare.subst(msrDCCIVACIop); decoder_output += DCStore64Constructor.subst(msrDCCIVACIop); exec_output += DCStore64Execute.subst(msrDCCIVACIop); @@ -497,13 +498,13 @@ let {{ EA &= ~(op_size - 1); ''' - msrDCIVACIop = InstObjParams("dc ivac", "Dcivac", "SysDC64", - { "ea_code" : msrdcivac_ea_code, - "memacc_code" : ';', - "use_uops" : 0, - "op_wb" : ";", - "fa_code" : cachem_fa}, - ['IsStore']); + msrDCIVACIop = ArmInstObjParams("dc ivac", "Dcivac", "SysDC64", + { "ea_code" : msrdcivac_ea_code, + "memacc_code" : ';', + "use_uops" : 0, + "op_wb" : ";", + "fa_code" : cachem_fa}, + ['IsStore']); header_output += DCStore64Declare.subst(msrDCIVACIop); decoder_output += DCStore64Constructor.subst(msrDCIVACIop); exec_output += DCStore64Execute.subst(msrDCIVACIop); @@ -533,9 +534,9 @@ let {{ } ''' - msrIop = InstObjParams("msr", inst_name, "MiscRegImmOp64", - msrImmPermission + code, - ["IsSerializeAfter", "IsNonSpeculative"]) + msrIop = ArmInstObjParams("msr", inst_name, "MiscRegImmOp64", + msrImmPermission + code, + ["IsSerializeAfter", "IsNonSpeculative"]) header_output += MiscRegOp64Declare.subst(msrIop) decoder_output += MiscRegOp64Constructor.subst(msrIop) exec_output += BasicExecute.subst(msrIop) @@ -561,8 +562,8 @@ let {{ def buildDataXCompInst(mnem, instType, suffix, code): global header_output, decoder_output, exec_output templateBase = "DataXCond%s" % instType - iop = InstObjParams(mnem, mnem.capitalize() + suffix + "64", - templateBase + "Op", code) + iop = ArmInstObjParams(mnem, mnem.capitalize() + suffix + "64", + templateBase + "Op", code) header_output += eval(templateBase + "Declare").subst(iop) decoder_output += eval(templateBase + "Constructor").subst(iop) exec_output += BasicExecute.subst(iop) diff --git a/src/arch/arm/isa/insts/div.isa b/src/arch/arm/isa/insts/div.isa index 57015692f..08f5c5f71 100644 --- a/src/arch/arm/isa/insts/div.isa +++ b/src/arch/arm/isa/insts/div.isa @@ -45,7 +45,7 @@ let {{ Dest_sw = Op1_sw / Op2_sw; } ''' - sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp", + sdivIop = ArmInstObjParams("sdiv", "Sdiv", "RegRegRegOp", { "code": sdivCode, "predicate_test": predicateTest, "op_class": "IntDivOp"}, []) @@ -60,7 +60,7 @@ let {{ Dest_uw = Op1_uw / Op2_uw; } ''' - udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp", + udivIop = ArmInstObjParams("udiv", "Udiv", "RegRegRegOp", { "code": udivCode, "predicate_test": predicateTest, "op_class": "IntDivOp"}, []) diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index 90525c07c..7f530c2b7 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -185,11 +185,11 @@ let {{ MiscDest = Op1; ''' - vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegImmOp", - { "code": vmsrCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, - ["IsSerializeAfter","IsNonSpeculative"]) + vmsrIop = ArmInstObjParams("vmsr", "Vmsr", "FpRegRegImmOp", + { "code": vmsrCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, + ["IsSerializeAfter","IsNonSpeculative"]) header_output += FpRegRegImmOpDeclare.subst(vmsrIop); decoder_output += FpRegRegImmOpConstructor.subst(vmsrIop); exec_output += PredOpExecute.subst(vmsrIop); @@ -198,12 +198,12 @@ let {{ Fpscr = Op1 & ~FpCondCodesMask; FpCondCodes = Op1 & FpCondCodesMask; ''' - vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp", - { "code": vmsrFpscrCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, - ["IsSerializeAfter","IsNonSpeculative", - "IsSquashAfter"]) + vmsrFpscrIop = ArmInstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp", + { "code": vmsrFpscrCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, + ["IsSerializeAfter","IsNonSpeculative", + "IsSquashAfter"]) header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop); decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop); exec_output += PredOpExecute.subst(vmsrFpscrIop); @@ -230,21 +230,21 @@ let {{ Dest = MiscOp1; ''' - vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegImmOp", - { "code": vmrsCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, - ["IsSerializeBefore"]) + vmrsIop = ArmInstObjParams("vmrs", "Vmrs", "FpRegRegImmOp", + { "code": vmrsCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, + ["IsSerializeBefore"]) header_output += FpRegRegImmOpDeclare.subst(vmrsIop); decoder_output += FpRegRegImmOpConstructor.subst(vmrsIop); exec_output += PredOpExecute.subst(vmrsIop); - vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp", - { "code": vmrsEnabledCheckCode + \ - "Dest = Fpscr | FpCondCodes;", - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, - ["IsSerializeBefore"]) + vmrsFpscrIop = ArmInstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp", + { "code": vmrsEnabledCheckCode + \ + "Dest = Fpscr | FpCondCodes;", + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, + ["IsSerializeBefore"]) header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop); decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); exec_output += PredOpExecute.subst(vmrsFpscrIop); @@ -255,10 +255,10 @@ let {{ CondCodesC = fpscr.c; CondCodesV = fpscr.v; ''' - vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "PredOp", - { "code": vmrsApsrFpscrCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }) + vmrsApsrFpscrIop = ArmInstObjParams("vmrs", "VmrsApsrFpscr", "PredOp", + { "code": vmrsApsrFpscrCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }) header_output += BasicDeclare.subst(vmrsApsrFpscrIop); decoder_output += BasicConstructor.subst(vmrsApsrFpscrIop); exec_output += PredOpExecute.subst(vmrsApsrFpscrIop); @@ -266,10 +266,10 @@ let {{ vmovImmSCode = vfpEnabledCheckCode + ''' FpDest_uw = bits(imm, 31, 0); ''' - vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp", - { "code": vmovImmSCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + vmovImmSIop = ArmInstObjParams("vmov", "VmovImmS", "FpRegImmOp", + { "code": vmovImmSCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, []) header_output += FpRegImmOpDeclare.subst(vmovImmSIop); decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop); exec_output += PredOpExecute.subst(vmovImmSIop); @@ -278,10 +278,10 @@ let {{ FpDestP0_uw = bits(imm, 31, 0); FpDestP1_uw = bits(imm, 63, 32); ''' - vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp", - { "code": vmovImmDCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + vmovImmDIop = ArmInstObjParams("vmov", "VmovImmD", "FpRegImmOp", + { "code": vmovImmDCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, []) header_output += FpRegImmOpDeclare.subst(vmovImmDIop); decoder_output += FpRegImmOpConstructor.subst(vmovImmDIop); exec_output += PredOpExecute.subst(vmovImmDIop); @@ -292,10 +292,10 @@ let {{ FpDestP2_uw = bits(imm, 31, 0); FpDestP3_uw = bits(imm, 63, 32); ''' - vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp", - { "code": vmovImmQCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + vmovImmQIop = ArmInstObjParams("vmov", "VmovImmQ", "FpRegImmOp", + { "code": vmovImmQCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, []) header_output += FpRegImmOpDeclare.subst(vmovImmQIop); decoder_output += FpRegImmOpConstructor.subst(vmovImmQIop); exec_output += PredOpExecute.subst(vmovImmQIop); @@ -303,10 +303,10 @@ let {{ vmovRegSCode = vfpEnabledCheckCode + ''' FpDest_uw = FpOp1_uw; ''' - vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp", - { "code": vmovRegSCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + vmovRegSIop = ArmInstObjParams("vmov", "VmovRegS", "FpRegRegOp", + { "code": vmovRegSCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, []) header_output += FpRegRegOpDeclare.subst(vmovRegSIop); decoder_output += FpRegRegOpConstructor.subst(vmovRegSIop); exec_output += PredOpExecute.subst(vmovRegSIop); @@ -315,10 +315,10 @@ let {{ FpDestP0_uw = FpOp1P0_uw; FpDestP1_uw = FpOp1P1_uw; ''' - vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp", - { "code": vmovRegDCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + vmovRegDIop = ArmInstObjParams("vmov", "VmovRegD", "FpRegRegOp", + { "code": vmovRegDCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, []) header_output += FpRegRegOpDeclare.subst(vmovRegDIop); decoder_output += FpRegRegOpConstructor.subst(vmovRegDIop); exec_output += PredOpExecute.subst(vmovRegDIop); @@ -329,10 +329,10 @@ let {{ FpDestP2_uw = FpOp1P2_uw; FpDestP3_uw = FpOp1P3_uw; ''' - vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp", - { "code": vmovRegQCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + vmovRegQIop = ArmInstObjParams("vmov", "VmovRegQ", "FpRegRegOp", + { "code": vmovRegQCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, []) header_output += FpRegRegOpDeclare.subst(vmovRegQIop); decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop); exec_output += PredOpExecute.subst(vmovRegQIop); @@ -340,10 +340,10 @@ let {{ vmovCoreRegBCode = simdEnabledCheckCode + ''' FpDest_uw = insertBits(FpDest_uw, imm * 8 + 7, imm * 8, Op1_ub); ''' - vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp", - { "code": vmovCoreRegBCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + vmovCoreRegBIop = ArmInstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp", + { "code": vmovCoreRegBCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop); decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop); exec_output += PredOpExecute.subst(vmovCoreRegBIop); @@ -351,10 +351,10 @@ let {{ vmovCoreRegHCode = simdEnabledCheckCode + ''' FpDest_uw = insertBits(FpDest_uw, imm * 16 + 15, imm * 16, Op1_uh); ''' - vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp", - { "code": vmovCoreRegHCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + vmovCoreRegHIop = ArmInstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp", + { "code": vmovCoreRegHCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop); decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop); exec_output += PredOpExecute.subst(vmovCoreRegHIop); @@ -362,10 +362,10 @@ let {{ vmovCoreRegWCode = vfpEnabledCheckCode + ''' FpDest_uw = Op1_uw; ''' - vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp", - { "code": vmovCoreRegWCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + vmovCoreRegWIop = ArmInstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp", + { "code": vmovCoreRegWCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, []) header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop); decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop); exec_output += PredOpExecute.subst(vmovCoreRegWIop); @@ -374,10 +374,11 @@ let {{ assert(imm < 4); Dest = bits(FpOp1_uw, imm * 8 + 7, imm * 8); ''' - vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp", - { "code": vmovRegCoreUBCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + vmovRegCoreUBIop = ArmInstObjParams( + "vmov", "VmovRegCoreUB", "FpRegRegImmOp", + { "code": vmovRegCoreUBCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); exec_output += PredOpExecute.subst(vmovRegCoreUBIop); @@ -386,10 +387,11 @@ let {{ assert(imm < 2); Dest = bits(FpOp1_uw, imm * 16 + 15, imm * 16); ''' - vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp", - { "code": vmovRegCoreUHCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + vmovRegCoreUHIop = ArmInstObjParams( + "vmov", "VmovRegCoreUH", "FpRegRegImmOp", + { "code": vmovRegCoreUHCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); exec_output += PredOpExecute.subst(vmovRegCoreUHIop); @@ -398,10 +400,11 @@ let {{ assert(imm < 4); Dest = sext<8>(bits(FpOp1_uw, imm * 8 + 7, imm * 8)); ''' - vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp", - { "code": vmovRegCoreSBCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + vmovRegCoreSBIop = ArmInstObjParams( + "vmov", "VmovRegCoreSB", "FpRegRegImmOp", + { "code": vmovRegCoreSBCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); exec_output += PredOpExecute.subst(vmovRegCoreSBIop); @@ -410,10 +413,11 @@ let {{ assert(imm < 2); Dest = sext<16>(bits(FpOp1_uw, imm * 16 + 15, imm * 16)); ''' - vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp", - { "code": vmovRegCoreSHCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + vmovRegCoreSHIop = ArmInstObjParams( + "vmov", "VmovRegCoreSH", "FpRegRegImmOp", + { "code": vmovRegCoreSHCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); exec_output += PredOpExecute.subst(vmovRegCoreSHIop); @@ -421,10 +425,10 @@ let {{ vmovRegCoreWCode = vfpEnabledCheckCode + ''' Dest = FpOp1_uw; ''' - vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp", - { "code": vmovRegCoreWCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + vmovRegCoreWIop = ArmInstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp", + { "code": vmovRegCoreWCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, []) header_output += FpRegRegOpDeclare.subst(vmovRegCoreWIop); decoder_output += FpRegRegOpConstructor.subst(vmovRegCoreWIop); exec_output += PredOpExecute.subst(vmovRegCoreWIop); @@ -433,10 +437,11 @@ let {{ FpDestP0_uw = Op1_uw; FpDestP1_uw = Op2_uw; ''' - vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp", - { "code": vmov2Reg2CoreCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + vmov2Reg2CoreIop = ArmInstObjParams( + "vmov", "Vmov2Reg2Core", "FpRegRegRegOp", + { "code": vmov2Reg2CoreCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, []) header_output += FpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); decoder_output += FpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); @@ -445,10 +450,11 @@ let {{ Dest_uw = FpOp2P0_uw; Op1_uw = FpOp2P1_uw; ''' - vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp", - { "code": vmov2Core2RegCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + vmov2Core2RegIop = ArmInstObjParams( + "vmov", "Vmov2Core2Reg", "FpRegRegRegOp", + { "code": vmov2Core2RegCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMiscOp" }, []) header_output += FpRegRegRegOpDeclare.subst(vmov2Core2RegIop); decoder_output += FpRegRegRegOpConstructor.subst(vmov2Core2RegIop); exec_output += PredOpExecute.subst(vmov2Core2RegIop); @@ -515,12 +521,12 @@ let {{ global header_output, decoder_output, exec_output code = singleTernOp % { "op": singleOp, "palam": paramStr } - sIop = InstObjParams(Name.lower() + "s", Name + "S", base, + sIop = ArmInstObjParams(Name.lower() + "s", Name + "S", base, { "code": code, "predicate_test": predicateTest, "op_class": opClass }, []) code = doubleTernOp % { "op": doubleOp, "palam": paramStr } - dIop = InstObjParams(Name.lower() + "d", Name + "D", base, + dIop = ArmInstObjParams(Name.lower() + "d", Name + "D", base, { "code": code, "predicate_test": predicateTest, "op_class": opClass }, []) @@ -547,13 +553,13 @@ let {{ code = singleCode % { "op": singleBinOp } code = code % { "func": singleOp } - sIop = InstObjParams(name + "s", Name + "S", base, + sIop = ArmInstObjParams(name + "s", Name + "S", base, { "code": code, "predicate_test": predicateTest, "op_class": opClass }, []) code = doubleCode % { "op": doubleBinOp } code = code % { "func": doubleOp } - dIop = InstObjParams(name + "d", Name + "D", base, + dIop = ArmInstObjParams(name + "d", Name + "D", base, { "code": code, "predicate_test": predicateTest, "op_class": opClass }, []) @@ -615,7 +621,7 @@ let {{ FpscrExc = fpscr; ''' ) - iop = InstObjParams( + iop = ArmInstObjParams( name + size_suffix, Name + size_suffix.upper(), base, @@ -642,13 +648,13 @@ let {{ code = singleCode % { "op": singleUnaryOp } code = code % { "func": singleOp } - sIop = InstObjParams(name + "s", Name + "S", base, + sIop = ArmInstObjParams(name + "s", Name + "S", base, { "code": code, "predicate_test": predicateTest, "op_class": opClass }, []) code = doubleCode % { "op": doubleUnaryOp } code = code % { "func": doubleOp } - dIop = InstObjParams(name + "d", Name + "D", base, + dIop = ArmInstObjParams(name + "d", Name + "D", base, { "code": code, "predicate_test": predicateTest, "op_class": opClass }, []) @@ -670,11 +676,11 @@ let {{ doubleOp = singleOp global header_output, decoder_output, exec_output - sIop = InstObjParams(name + "s", Name + "S", base, + sIop = ArmInstObjParams(name + "s", Name + "S", base, { "code": singleSimpleCode % { "op": singleOp }, "predicate_test": predicateTest, "op_class": opClass }, []) - dIop = InstObjParams(name + "d", Name + "D", base, + dIop = ArmInstObjParams(name + "d", Name + "D", base, { "code": doubleCode % { "op": doubleOp }, "predicate_test": predicateTest, "op_class": opClass }, []) @@ -727,7 +733,7 @@ let {{ fpscr.fz, fpscr.dn, fpscr.rMode); FpscrExc = fpscr; ''' - vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp", + vmlaSIop = ArmInstObjParams("vmlas", "VmlaS", "FpRegRegRegOp", { "code": vmlaSCode, "predicate_test": predicateTest, "op_class": "SimdFloatMultAccOp" }, []) @@ -747,7 +753,7 @@ let {{ FpDestP1_uw = dblHi(dest); FpscrExc = fpscr; ''' - vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp", + vmlaDIop = ArmInstObjParams("vmlad", "VmlaD", "FpRegRegRegOp", { "code": vmlaDCode, "predicate_test": predicateTest, "op_class": "SimdFloatMultAccOp" }, []) @@ -763,7 +769,7 @@ let {{ fpscr.fz, fpscr.dn, fpscr.rMode); FpscrExc = fpscr; ''' - vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp", + vmlsSIop = ArmInstObjParams("vmlss", "VmlsS", "FpRegRegRegOp", { "code": vmlsSCode, "predicate_test": predicateTest, "op_class": "SimdFloatMultAccOp" }, []) @@ -783,7 +789,7 @@ let {{ FpDestP1_uw = dblHi(dest); FpscrExc = fpscr; ''' - vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp", + vmlsDIop = ArmInstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp", { "code": vmlsDCode, "predicate_test": predicateTest, "op_class": "SimdFloatMultAccOp" }, []) @@ -799,7 +805,7 @@ let {{ fpscr.fz, fpscr.dn, fpscr.rMode); FpscrExc = fpscr; ''' - vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp", + vnmlaSIop = ArmInstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp", { "code": vnmlaSCode, "predicate_test": predicateTest, "op_class": "SimdFloatMultAccOp" }, []) @@ -819,7 +825,7 @@ let {{ FpDestP1_uw = dblHi(dest); FpscrExc = fpscr; ''' - vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp", + vnmlaDIop = ArmInstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp", { "code": vnmlaDCode, "predicate_test": predicateTest, "op_class": "SimdFloatMultAccOp" }, []) @@ -835,10 +841,10 @@ let {{ fpscr.fz, fpscr.dn, fpscr.rMode); FpscrExc = fpscr; ''' - vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp", - { "code": vnmlsSCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMultAccOp" }, []) + vnmlsSIop = ArmInstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp", + { "code": vnmlsSCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMultAccOp" }, []) header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop); decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop); exec_output += PredOpExecute.subst(vnmlsSIop); @@ -855,10 +861,10 @@ let {{ FpDestP1_uw = dblHi(dest); FpscrExc = fpscr; ''' - vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp", - { "code": vnmlsDCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMultAccOp" }, []) + vnmlsDIop = ArmInstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp", + { "code": vnmlsDCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMultAccOp" }, []) header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop); decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop); exec_output += PredOpExecute.subst(vnmlsDIop); @@ -869,10 +875,10 @@ let {{ fpscr.fz, fpscr.dn, fpscr.rMode); FpscrExc = fpscr; ''' - vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp", - { "code": vnmulSCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMultOp" }, []) + vnmulSIop = ArmInstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp", + { "code": vnmulSCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatMultOp" }, []) header_output += FpRegRegRegOpDeclare.subst(vnmulSIop); decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop); exec_output += PredOpExecute.subst(vnmulSIop); @@ -887,7 +893,7 @@ let {{ FpDestP1_uw = dblHi(dest); FpscrExc = fpscr; ''' - vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp", + vnmulDIop = ArmInstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp", { "code": vnmulDCode, "predicate_test": predicateTest, "op_class": "SimdFloatMultOp" }, []) @@ -911,10 +917,10 @@ let {{ finishVfp(fpscr, state, fpscr.fz); FpscrExc = fpscr; ''' - vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", - { "code": vcvtUIntFpSCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtUIntFpSIop = ArmInstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", + { "code": vcvtUIntFpSCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop); decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop); exec_output += PredOpExecute.subst(vcvtUIntFpSIop); @@ -930,10 +936,10 @@ let {{ FpDestP1_uw = dblHi(cDest); FpscrExc = fpscr; ''' - vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", - { "code": vcvtUIntFpDCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtUIntFpDIop = ArmInstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", + { "code": vcvtUIntFpDCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop); decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop); exec_output += PredOpExecute.subst(vcvtUIntFpDIop); @@ -947,10 +953,10 @@ let {{ finishVfp(fpscr, state, fpscr.fz); FpscrExc = fpscr; ''' - vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", - { "code": vcvtSIntFpSCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtSIntFpSIop = ArmInstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", + { "code": vcvtSIntFpSCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop); decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop); exec_output += PredOpExecute.subst(vcvtSIntFpSIop); @@ -966,10 +972,10 @@ let {{ FpDestP1_uw = dblHi(cDest); FpscrExc = fpscr; ''' - vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", - { "code": vcvtSIntFpDCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtSIntFpDIop = ArmInstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", + { "code": vcvtSIntFpDCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop); decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); exec_output += PredOpExecute.subst(vcvtSIntFpDIop); @@ -984,10 +990,11 @@ let {{ FpCondCodes = fpscr & FpCondCodesMask; FpscrExc = fpscr; ''' - vjcvtSFixedFpDIop = InstObjParams("vjcvt", "VjcvtSFixedFpD", "FpRegRegOp", - { "code": vjcvtSFixedFpDCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vjcvtSFixedFpDIop = ArmInstObjParams( + "vjcvt", "VjcvtSFixedFpD", "FpRegRegOp", + { "code": vjcvtSFixedFpDCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegOpDeclare.subst(vjcvtSFixedFpDIop); decoder_output += FpRegRegOpConstructor.subst(vjcvtSFixedFpDIop); exec_output += PredOpExecute.subst(vjcvtSFixedFpDIop); @@ -1002,10 +1009,10 @@ let {{ finishVfp(fpscr, state, fpscr.fz); FpscrExc = fpscr; ''' - vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", - { "code": vcvtFpUIntSRCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtFpUIntSRIop = ArmInstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", + { "code": vcvtFpUIntSRCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); @@ -1022,10 +1029,10 @@ let {{ FpDestP0_uw = result; FpscrExc = fpscr; ''' - vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", - { "code": vcvtFpUIntDRCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtFpUIntDRIop = ArmInstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", + { "code": vcvtFpUIntDRCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); @@ -1040,10 +1047,10 @@ let {{ finishVfp(fpscr, state, fpscr.fz); FpscrExc = fpscr; ''' - vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", - { "code": vcvtFpSIntSRCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtFpSIntSRIop = ArmInstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", + { "code": vcvtFpSIntSRCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); @@ -1060,10 +1067,10 @@ let {{ FpDestP0_uw = result; FpscrExc = fpscr; ''' - vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", - { "code": vcvtFpSIntDRCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtFpSIntDRIop = ArmInstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", + { "code": vcvtFpSIntDRCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); @@ -1082,7 +1089,7 @@ let {{ full_code = vfpEnabledCheckCode + code.format( round_mode=round_mode_suffix_to_mode[roundModeSuffix], ) - iop = InstObjParams( + iop = ArmInstObjParams( "vcvt{}".format(roundModeSuffix), className.format(roundModeSuffix), "FpRegRegOp", @@ -1171,7 +1178,7 @@ let {{ FpDestP1_uw = dblHi(cDest); FpscrExc = fpscr; ''' - vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", + vcvtFpSFpDIop = ArmInstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", { "code": vcvtFpSFpDCode, "predicate_test": predicateTest, "op_class": "SimdFloatCvtOp" }, []) @@ -1190,7 +1197,7 @@ let {{ finishVfp(fpscr, state, fpscr.fz); FpscrExc = fpscr; ''' - vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", + vcvtFpDFpSIop = ArmInstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", { "code": vcvtFpDFpSCode, "predicate_test": predicateTest, "op_class": "SimdFloatCvtOp" }, []) @@ -1209,10 +1216,10 @@ let {{ finishVfp(fpscr, state, fpscr.fz); FpscrExc = fpscr; ''' - vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp", - { "code": vcvtFpHTFpSCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtFpHTFpSIop = ArmInstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp", + { "code": vcvtFpHTFpSCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop); decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop); exec_output += PredOpExecute.subst(vcvtFpHTFpSIop); @@ -1227,10 +1234,10 @@ let {{ finishVfp(fpscr, state, fpscr.fz); FpscrExc = fpscr; ''' - vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp", - { "code": vcvtFpHBFpSCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtFpHBFpSIop = ArmInstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp", + { "code": vcvtFpHBFpSCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop); decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop); exec_output += PredOpExecute.subst(vcvtFpHBFpSIop); @@ -1248,10 +1255,10 @@ let {{ finishVfp(fpscr, state, fpscr.fz); FpscrExc = fpscr; ''' - vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp", - { "code": vcvtFpHTFpSCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtFpSFpHTIop = ArmInstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp", + { "code": vcvtFpHTFpSCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop); decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop); exec_output += PredOpExecute.subst(vcvtFpSFpHTIop); @@ -1269,10 +1276,10 @@ let {{ finishVfp(fpscr, state, fpscr.fz); FpscrExc = fpscr; ''' - vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp", - { "code": vcvtFpSFpHBCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtFpSFpHBIop = ArmInstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp", + { "code": vcvtFpSFpHBCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop); decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop); exec_output += PredOpExecute.subst(vcvtFpSFpHBIop); @@ -1299,7 +1306,7 @@ let {{ FpCondCodes = fpscr & FpCondCodesMask; FpscrExc = fpscr; ''' - vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", + vcmpSIop = ArmInstObjParams("vcmps", "VcmpS", "FpRegRegOp", { "code": vcmpSCode, "predicate_test": predicateTest, "op_class": "SimdFloatCmpOp" }, []) @@ -1331,7 +1338,7 @@ let {{ FpCondCodes = fpscr & FpCondCodesMask; FpscrExc = fpscr; ''' - vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", + vcmpDIop = ArmInstObjParams("vcmpd", "VcmpD", "FpRegRegOp", { "code": vcmpDCode, "predicate_test": predicateTest, "op_class": "SimdFloatCmpOp" }, []) @@ -1361,7 +1368,7 @@ let {{ FpCondCodes = fpscr & FpCondCodesMask; FpscrExc = fpscr; ''' - vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", + vcmpZeroSIop = ArmInstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", { "code": vcmpZeroSCode, "predicate_test": predicateTest, "op_class": "SimdFloatCmpOp" }, []) @@ -1392,7 +1399,7 @@ let {{ FpCondCodes = fpscr & FpCondCodesMask; FpscrExc = fpscr; ''' - vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", + vcmpZeroDIop = ArmInstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", { "code": vcmpZeroDCode, "predicate_test": predicateTest, "op_class": "SimdFloatCmpOp" }, []) @@ -1416,7 +1423,7 @@ let {{ FpCondCodes = fpscr & FpCondCodesMask; FpscrExc = fpscr; ''' - vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", + vcmpeSIop = ArmInstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", { "code": vcmpeSCode, "predicate_test": predicateTest, "op_class": "SimdFloatCmpOp" }, []) @@ -1442,7 +1449,7 @@ let {{ FpCondCodes = fpscr & FpCondCodesMask; FpscrExc = fpscr; ''' - vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", + vcmpeDIop = ArmInstObjParams("vcmped", "VcmpeD", "FpRegRegOp", { "code": vcmpeDCode, "predicate_test": predicateTest, "op_class": "SimdFloatCmpOp" }, []) @@ -1466,7 +1473,7 @@ let {{ FpCondCodes = fpscr & FpCondCodesMask; FpscrExc = fpscr; ''' - vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", + vcmpeZeroSIop = ArmInstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", { "code": vcmpeZeroSCode, "predicate_test": predicateTest, "op_class": "SimdFloatCmpOp" }, []) @@ -1491,7 +1498,7 @@ let {{ FpCondCodes = fpscr & FpCondCodesMask; FpscrExc = fpscr; ''' - vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", + vcmpeZeroDIop = ArmInstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", { "code": vcmpeZeroDCode, "predicate_test": predicateTest, "op_class": "SimdFloatCmpOp" }, []) @@ -1513,10 +1520,10 @@ let {{ FpDest = FpOp2; } ''' - vselSIop = InstObjParams("vsels", "VselS", "FpRegRegRegCondOp", - { "code" : vselSCode, - "predicate_test" : predicateTest, - "op_class" : "SimdFloatCmpOp" }, [] ) + vselSIop = ArmInstObjParams("vsels", "VselS", "FpRegRegRegCondOp", + { "code" : vselSCode, + "predicate_test" : predicateTest, + "op_class" : "SimdFloatCmpOp" }, [] ) header_output += FpRegRegRegCondOpDeclare.subst(vselSIop); decoder_output += FpRegRegRegCondOpConstructor.subst(vselSIop); exec_output += PredOpExecute.subst(vselSIop); @@ -1530,10 +1537,10 @@ let {{ FpDestP1_uw = FpOp2P1_uw; } ''' - vselDIop = InstObjParams("vseld", "VselD", "FpRegRegRegCondOp", - { "code" : vselDCode, - "predicate_test" : predicateTest, - "op_class" : "SimdFloatCmpOp" }, [] ) + vselDIop = ArmInstObjParams("vseld", "VselD", "FpRegRegRegCondOp", + { "code" : vselDCode, + "predicate_test" : predicateTest, + "op_class" : "SimdFloatCmpOp" }, [] ) header_output += FpRegRegRegCondOpDeclare.subst(vselDIop); decoder_output += FpRegRegRegCondOpConstructor.subst(vselDIop); exec_output += PredOpExecute.subst(vselDIop); @@ -1556,10 +1563,11 @@ let {{ finishVfp(fpscr, state, fpscr.fz); FpscrExc = fpscr; ''' - vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", - { "code": vcvtFpSFixedSCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtFpSFixedSIop = ArmInstObjParams( + "vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", + { "code": vcvtFpSFixedSCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); @@ -1577,10 +1585,11 @@ let {{ FpDestP1_uw = mid >> 32; FpscrExc = fpscr; ''' - vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", - { "code": vcvtFpSFixedDCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtFpSFixedDIop = ArmInstObjParams( + "vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", + { "code": vcvtFpSFixedDCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); @@ -1595,10 +1604,11 @@ let {{ finishVfp(fpscr, state, fpscr.fz); FpscrExc = fpscr; ''' - vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", - { "code": vcvtFpUFixedSCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtFpUFixedSIop = ArmInstObjParams( + "vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", + { "code": vcvtFpUFixedSCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); @@ -1616,10 +1626,11 @@ let {{ FpDestP1_uw = mid >> 32; FpscrExc = fpscr; ''' - vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", - { "code": vcvtFpUFixedDCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtFpUFixedDIop = ArmInstObjParams( + "vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", + { "code": vcvtFpUFixedDCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); @@ -1633,10 +1644,11 @@ let {{ finishVfp(fpscr, state, fpscr.fz); FpscrExc = fpscr; ''' - vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", - { "code": vcvtSFixedFpSCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtSFixedFpSIop = ArmInstObjParams( + "vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", + { "code": vcvtSFixedFpSCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); @@ -1653,10 +1665,11 @@ let {{ FpDestP1_uw = dblHi(cDest); FpscrExc = fpscr; ''' - vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", - { "code": vcvtSFixedFpDCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtSFixedFpDIop = ArmInstObjParams( + "vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", + { "code": vcvtSFixedFpDCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); @@ -1670,10 +1683,11 @@ let {{ finishVfp(fpscr, state, fpscr.fz); FpscrExc = fpscr; ''' - vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", - { "code": vcvtUFixedFpSCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtUFixedFpSIop = ArmInstObjParams( + "vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", + { "code": vcvtUFixedFpSCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); @@ -1690,10 +1704,11 @@ let {{ FpDestP1_uw = dblHi(cDest); FpscrExc = fpscr; ''' - vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", - { "code": vcvtUFixedFpDCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtUFixedFpDIop = ArmInstObjParams( + "vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", + { "code": vcvtUFixedFpDCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); @@ -1708,11 +1723,11 @@ let {{ finishVfp(fpscr, state, fpscr.fz); FpscrExc = fpscr; ''' - vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", - "FpRegRegImmOp", - { "code": vcvtFpSHFixedSCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtFpSHFixedSIop = ArmInstObjParams("vcvt", "VcvtFpSHFixedS", + "FpRegRegImmOp", + { "code": vcvtFpSHFixedSCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); @@ -1730,11 +1745,11 @@ let {{ FpDestP1_uw = result >> 32; FpscrExc = fpscr; ''' - vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", - "FpRegRegImmOp", - { "code": vcvtFpSHFixedDCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtFpSHFixedDIop = ArmInstObjParams("vcvt", "VcvtFpSHFixedD", + "FpRegRegImmOp", + { "code": vcvtFpSHFixedDCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); @@ -1749,11 +1764,11 @@ let {{ finishVfp(fpscr, state, fpscr.fz); FpscrExc = fpscr; ''' - vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", - "FpRegRegImmOp", - { "code": vcvtFpUHFixedSCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtFpUHFixedSIop = ArmInstObjParams("vcvt", "VcvtFpUHFixedS", + "FpRegRegImmOp", + { "code": vcvtFpUHFixedSCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); @@ -1771,11 +1786,11 @@ let {{ FpDestP1_uw = mid >> 32; FpscrExc = fpscr; ''' - vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", - "FpRegRegImmOp", - { "code": vcvtFpUHFixedDCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtFpUHFixedDIop = ArmInstObjParams("vcvt", "VcvtFpUHFixedD", + "FpRegRegImmOp", + { "code": vcvtFpUHFixedDCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); @@ -1789,11 +1804,11 @@ let {{ finishVfp(fpscr, state, fpscr.fz); FpscrExc = fpscr; ''' - vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", - "FpRegRegImmOp", - { "code": vcvtSHFixedFpSCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtSHFixedFpSIop = ArmInstObjParams("vcvt", "VcvtSHFixedFpS", + "FpRegRegImmOp", + { "code": vcvtSHFixedFpSCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); @@ -1810,11 +1825,11 @@ let {{ FpDestP1_uw = dblHi(cDest); FpscrExc = fpscr; ''' - vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", - "FpRegRegImmOp", - { "code": vcvtSHFixedFpDCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtSHFixedFpDIop = ArmInstObjParams("vcvt", "VcvtSHFixedFpD", + "FpRegRegImmOp", + { "code": vcvtSHFixedFpDCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); @@ -1828,11 +1843,11 @@ let {{ finishVfp(fpscr, state, fpscr.fz); FpscrExc = fpscr; ''' - vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", - "FpRegRegImmOp", - { "code": vcvtUHFixedFpSCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtUHFixedFpSIop = ArmInstObjParams("vcvt", "VcvtUHFixedFpS", + "FpRegRegImmOp", + { "code": vcvtUHFixedFpSCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); @@ -1849,11 +1864,11 @@ let {{ FpDestP1_uw = dblHi(cDest); FpscrExc = fpscr; ''' - vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", - "FpRegRegImmOp", - { "code": vcvtUHFixedFpDCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatCvtOp" }, []) + vcvtUHFixedFpDIop = ArmInstObjParams("vcvt", "VcvtUHFixedFpD", + "FpRegRegImmOp", + { "code": vcvtUHFixedFpDCode, + "predicate_test": predicateTest, + "op_class": "SimdFloatCvtOp" }, []) header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); diff --git a/src/arch/arm/isa/insts/fp64.isa b/src/arch/arm/isa/insts/fp64.isa index a7b76eadf..0c010ceb9 100644 --- a/src/arch/arm/isa/insts/fp64.isa +++ b/src/arch/arm/isa/insts/fp64.isa @@ -52,9 +52,9 @@ let {{ AA64FpDestP2_uw = 0; AA64FpDestP3_uw = 0; ''' - fmovImmSIop = InstObjParams("fmov", "FmovImmS", "FpRegImmOp", - { "code": fmovImmSCode, - "op_class": "FloatMiscOp" }, []) + fmovImmSIop = ArmInstObjParams("fmov", "FmovImmS", "FpRegImmOp", + { "code": fmovImmSCode, + "op_class": "FloatMiscOp" }, []) fmovImmSIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" header_output += FpRegImmOpDeclare.subst(fmovImmSIop); decoder_output += FpRegImmOpConstructor.subst(fmovImmSIop); @@ -66,9 +66,9 @@ let {{ AA64FpDestP2_uw = 0; AA64FpDestP3_uw = 0; ''' - fmovImmDIop = InstObjParams("fmov", "FmovImmD", "FpRegImmOp", - { "code": fmovImmDCode, - "op_class": "FloatMiscOp" }, []) + fmovImmDIop = ArmInstObjParams("fmov", "FmovImmD", "FpRegImmOp", + { "code": fmovImmDCode, + "op_class": "FloatMiscOp" }, []) fmovImmDIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" header_output += FpRegImmOpDeclare.subst(fmovImmDIop); decoder_output += AA64FpRegImmOpConstructor.subst(fmovImmDIop); @@ -80,9 +80,9 @@ let {{ AA64FpDestP2_uw = 0; AA64FpDestP3_uw = 0; ''' - fmovRegSIop = InstObjParams("fmov", "FmovRegS", "FpRegRegOp", - { "code": fmovRegSCode, - "op_class": "FloatMiscOp" }, []) + fmovRegSIop = ArmInstObjParams("fmov", "FmovRegS", "FpRegRegOp", + { "code": fmovRegSCode, + "op_class": "FloatMiscOp" }, []) fmovRegSIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" header_output += FpRegRegOpDeclare.subst(fmovRegSIop); decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegSIop); @@ -94,9 +94,9 @@ let {{ AA64FpDestP2_uw = 0; AA64FpDestP3_uw = 0; ''' - fmovRegDIop = InstObjParams("fmov", "FmovRegD", "FpRegRegOp", - { "code": fmovRegDCode, - "op_class": "FloatMiscOp" }, []) + fmovRegDIop = ArmInstObjParams("fmov", "FmovRegD", "FpRegRegOp", + { "code": fmovRegDCode, + "op_class": "FloatMiscOp" }, []) fmovRegDIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" header_output += FpRegRegOpDeclare.subst(fmovRegDIop); decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegDIop); @@ -108,9 +108,9 @@ let {{ AA64FpDestP2_uw = 0; AA64FpDestP3_uw = 0; ''' - fmovCoreRegWIop = InstObjParams("fmov", "FmovCoreRegW", "FpRegRegOp", - { "code": fmovCoreRegWCode, - "op_class": "FloatMiscOp" }, []) + fmovCoreRegWIop = ArmInstObjParams("fmov", "FmovCoreRegW", "FpRegRegOp", + { "code": fmovCoreRegWCode, + "op_class": "FloatMiscOp" }, []) fmovCoreRegWIop.snippets["code"] += zeroSveVecRegUpperPartCode % \ "AA64FpDest" header_output += FpRegRegOpDeclare.subst(fmovCoreRegWIop); @@ -123,9 +123,9 @@ let {{ AA64FpDestP2_uw = 0; AA64FpDestP3_uw = 0; ''' - fmovCoreRegXIop = InstObjParams("fmov", "FmovCoreRegX", "FpRegRegOp", - { "code": fmovCoreRegXCode, - "op_class": "FloatMiscOp" }, []) + fmovCoreRegXIop = ArmInstObjParams("fmov", "FmovCoreRegX", "FpRegRegOp", + { "code": fmovCoreRegXCode, + "op_class": "FloatMiscOp" }, []) fmovCoreRegXIop.snippets["code"] += zeroSveVecRegUpperPartCode % \ "AA64FpDest" header_output += FpRegRegOpDeclare.subst(fmovCoreRegXIop); @@ -138,9 +138,9 @@ let {{ AA64FpDestP1_uw = AA64FpDestP1_uw; AA64FpDestP2_uw = XOp1_ud; AA64FpDestP3_uw = XOp1_ud >> 32;''' - fmovUCoreRegXIop = InstObjParams("fmov", "FmovUCoreRegX", "FpRegRegOp", - { "code": fmovUCoreRegXCode, - "op_class": "FloatMiscOp" }, []) + fmovUCoreRegXIop = ArmInstObjParams("fmov", "FmovUCoreRegX", "FpRegRegOp", + { "code": fmovUCoreRegXCode, + "op_class": "FloatMiscOp" }, []) fmovUCoreRegXIop.snippets["code"] += zeroSveVecRegUpperPartCode % \ "AA64FpDest" header_output += FpRegRegOpDeclare.subst(fmovUCoreRegXIop); @@ -150,9 +150,9 @@ let {{ fmovRegCoreWCode = vfp64EnabledCheckCode + ''' WDest = AA64FpOp1P0_uw; ''' - fmovRegCoreWIop = InstObjParams("fmov", "FmovRegCoreW", "FpRegRegOp", - { "code": fmovRegCoreWCode, - "op_class": "FloatMiscOp" }, []) + fmovRegCoreWIop = ArmInstObjParams("fmov", "FmovRegCoreW", "FpRegRegOp", + { "code": fmovRegCoreWCode, + "op_class": "FloatMiscOp" }, []) header_output += FpRegRegOpDeclare.subst(fmovRegCoreWIop); decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegCoreWIop); exec_output += BasicExecute.subst(fmovRegCoreWIop); @@ -160,9 +160,9 @@ let {{ fmovRegCoreXCode = vfp64EnabledCheckCode + ''' XDest = ( ((uint64_t) AA64FpOp1P1_uw) << 32) | AA64FpOp1P0_uw; ''' - fmovRegCoreXIop = InstObjParams("fmov", "FmovRegCoreX", "FpRegRegOp", - { "code": fmovRegCoreXCode, - "op_class": "FloatMiscOp" }, []) + fmovRegCoreXIop = ArmInstObjParams("fmov", "FmovRegCoreX", "FpRegRegOp", + { "code": fmovRegCoreXCode, + "op_class": "FloatMiscOp" }, []) header_output += FpRegRegOpDeclare.subst(fmovRegCoreXIop); decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegCoreXIop); exec_output += BasicExecute.subst(fmovRegCoreXIop); @@ -170,9 +170,9 @@ let {{ fmovURegCoreXCode = vfp64EnabledCheckCode + ''' XDest = ( ((uint64_t) AA64FpOp1P3_uw) << 32) | AA64FpOp1P2_uw; ''' - fmovURegCoreXIop = InstObjParams("fmov", "FmovURegCoreX", "FpRegRegOp", - { "code": fmovURegCoreXCode, - "op_class": "FloatMiscOp" }, []) + fmovURegCoreXIop = ArmInstObjParams("fmov", "FmovURegCoreX", "FpRegRegOp", + { "code": fmovURegCoreXCode, + "op_class": "FloatMiscOp" }, []) header_output += FpRegRegOpDeclare.subst(fmovURegCoreXIop); decoder_output += AA64FpRegRegOpConstructor.subst(fmovURegCoreXIop); exec_output += BasicExecute.subst(fmovURegCoreXIop); @@ -314,9 +314,9 @@ let {{ FpscrExc = fpscr; ''' - iop = InstObjParams(name.lower(), name + suffix, - "FpRegRegRegRegOp", - { "code": code, "op_class": opClass }, []) + iop = ArmInstObjParams(name.lower(), name + suffix, + "FpRegRegRegRegOp", + { "code": code, "op_class": opClass }, []) iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" header_output += AA64FpRegRegRegRegOpDeclare.subst(iop) @@ -347,19 +347,19 @@ let {{ global header_output, decoder_output, exec_output code = halfIntConvCode2 % { "op": halfOp } - hIop = InstObjParams(name, Name + "H", base, + hIop = ArmInstObjParams(name, Name + "H", base, { "code": code, "op_class": opClass }, []) hIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" code = singleIntConvCode2 % { "op": singleOp } - sIop = InstObjParams(name, Name + "S", base, + sIop = ArmInstObjParams(name, Name + "S", base, { "code": code, "op_class": opClass }, []) sIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" code = doubleIntConvCode2 % { "op": doubleOp } - dIop = InstObjParams(name, Name + "D", base, + dIop = ArmInstObjParams(name, Name + "D", base, { "code": code, "op_class": opClass }, []) dIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" @@ -416,17 +416,17 @@ let {{ global header_output, decoder_output, exec_output code = halfIntConvCode % { "op": halfOp } - hIop = InstObjParams(name, Name + "H", base, + hIop = ArmInstObjParams(name, Name + "H", base, { "code": code, "op_class": opClass }, []) hIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" code = singleIntConvCode % { "op": singleOp } - sIop = InstObjParams(name, Name + "S", base, + sIop = ArmInstObjParams(name, Name + "S", base, { "code": code, "op_class": opClass }, []) sIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" code = doubleIntConvCode % { "op": doubleOp } - dIop = InstObjParams(name, Name + "D", base, + dIop = ArmInstObjParams(name, Name + "D", base, { "code": code, "op_class": opClass }, []) dIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" @@ -462,7 +462,7 @@ let {{ for code, op, suffix in [[hCode, halfOp, "H"], [sCode, singleOp, "S"], [dCode, doubleOp, "D"]]: - iop = InstObjParams(name, Name + suffix, base, + iop = ArmInstObjParams(name, Name + suffix, base, { "code": code % { "op": op }, "op_class": opClass }, []) iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" @@ -552,9 +552,10 @@ let {{ instName = "Fcvt%s%sIntFp%s" %(regL, us, "D" if isDouble else "S") mnem = "%scvtf" %(us.lower()) - fcvtIntFpDIop = InstObjParams(mnem, instName, "FpRegRegOp", - { "code": fcvtIntFpDCode, - "op_class": "FloatCvtOp" }, []) + fcvtIntFpDIop = ArmInstObjParams(mnem, instName, "FpRegRegOp", + { "code": fcvtIntFpDCode, + "op_class": "FloatCvtOp" }, + []) fcvtIntFpDIop.snippets["code"] += \ zeroSveVecRegUpperPartCode % "AA64FpDest" @@ -594,9 +595,9 @@ let {{ "X" if isXReg else "W", "D" if isDouble else "S", rmode) mnem = "fcvt%s%s" %(rmode, "s" if isSigned else "u") - fcvtFpIntIop = InstObjParams(mnem, instName, "FpRegRegOp", - { "code": fcvtFpIntCode, - "op_class": "FloatCvtOp" }, []) + fcvtFpIntIop = ArmInstObjParams(mnem, instName, "FpRegRegOp", + { "code": fcvtFpIntCode, + "op_class": "FloatCvtOp" }, []) header_output += FpRegRegOpDeclare.subst(fcvtFpIntIop); decoder_output += FpRegRegOpConstructor.subst(fcvtFpIntIop); exec_output += BasicExecute.subst(fcvtFpIntIop); @@ -617,7 +618,7 @@ let {{ AA64FpDestP3_uw = 0; FpscrExc = fpscr; ''' - fcvtFpSFpDIop = InstObjParams("fcvt", "FCvtFpSFpD", "FpRegRegOp", + fcvtFpSFpDIop = ArmInstObjParams("fcvt", "FCvtFpSFpD", "FpRegRegOp", { "code": fcvtFpSFpDCode, "op_class": "FloatCvtOp" }, []) fcvtFpSFpDIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" @@ -635,9 +636,9 @@ let {{ AA64FpDestP3_uw = 0; FpscrExc = fpscr; ''' - fcvtFpDFpSIop = InstObjParams("fcvt", "FcvtFpDFpS", "FpRegRegOp", - {"code": fcvtFpDFpSCode, - "op_class": "FloatCvtOp" }, []) + fcvtFpDFpSIop = ArmInstObjParams("fcvt", "FcvtFpDFpS", "FpRegRegOp", + {"code": fcvtFpDFpSCode, + "op_class": "FloatCvtOp" }, []) fcvtFpDFpSIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" header_output += FpRegRegOpDeclare.subst(fcvtFpDFpSIop); decoder_output += AA64FpRegRegOpConstructor.subst(fcvtFpDFpSIop); @@ -668,9 +669,9 @@ let {{ ''' instName = "FcvtFpHFp%s" %("D" if isDouble else "S") - fcvtFpHFpIop = InstObjParams("fcvt", instName, "FpRegRegOp", - { "code": code, - "op_class": "FloatCvtOp" }, []) + fcvtFpHFpIop = ArmInstObjParams("fcvt", instName, "FpRegRegOp", + { "code": code, + "op_class": "FloatCvtOp" }, []) fcvtFpHFpIop.snippets["code"] += zeroSveVecRegUpperPartCode % \ "AA64FpDest" header_output += FpRegRegOpDeclare.subst(fcvtFpHFpIop); @@ -693,9 +694,9 @@ let {{ "64" if isDouble else "32") instName = "FcvtFp%sFpH" %("D" if isDouble else "S") - fcvtFpFpHIop = InstObjParams("fcvt", instName, "FpRegRegOp", - { "code": code, - "op_class": "FloatCvtOp" }, []) + fcvtFpFpHIop = ArmInstObjParams("fcvt", instName, "FpRegRegOp", + { "code": code, + "op_class": "FloatCvtOp" }, []) fcvtFpFpHIop.snippets["code"] += zeroSveVecRegUpperPartCode % \ "AA64FpDest" header_output += FpRegRegOpDeclare.subst(fcvtFpFpHIop); @@ -734,12 +735,12 @@ let {{ typeName = "Imm" if isImm else "Reg" instName = "FCmp%s%s%s" %("" if isQuiet else "E", typeName, "D" if isDouble else "S") - fcmpIop = InstObjParams("fcmp%s" %("" if isQuiet else "e"), instName, - "FpReg%sOp" %(typeName), - {"code": fcmpCode, - "op_class": "FloatCmpOp"}, []) + fcmpIop = ArmInstObjParams("fcmp%s" % ("" if isQuiet else "e"), + instName, "FpReg%sOp" % typeName, + { "code": fcmpCode, + "op_class": "FloatCmpOp"}, []) - declareTemp = eval("FpReg%sOpDeclare" %(typeName)); + declareTemp = eval("FpReg%sOpDeclare" %(typeName)); constructorTemp = eval("AA64FpReg%sOpConstructor" %(typeName)); header_output += declareTemp.subst(fcmpIop); decoder_output += constructorTemp.subst(fcmpIop); @@ -781,10 +782,10 @@ let {{ instName = "FCCmp%sReg%s" %("" if isQuiet else "E", "D" if isDouble else "S") - fccmpIop = InstObjParams("fccmp%s" %("" if isQuiet else "e"), - instName, "FpCondCompRegOp", - {"code": fccmpCode, - "op_class": "FloatCmpOp"}, []) + fccmpIop = ArmInstObjParams("fccmp%s" % ("" if isQuiet else "e"), + instName, "FpCondCompRegOp", + { "code" : fccmpCode, + "op_class" : "FloatCmpOp"}, []) header_output += DataXCondCompRegDeclare.subst(fccmpIop); decoder_output += DataXCondCompRegConstructor.subst(fccmpIop); exec_output += BasicExecute.subst(fccmpIop); @@ -827,9 +828,9 @@ let {{ "D" if isDouble else "S", "X" if isXReg else "W") mnem = "fcvtz%s" %("s" if isSigned else "u") - fcvtFpFixedIop = InstObjParams(mnem, instName, "FpRegRegImmOp", - { "code": fcvtFpFixedCode, - "op_class": "FloatCvtOp" }, []) + fcvtFpFixedIop = ArmInstObjParams(mnem, instName, "FpRegRegImmOp", + { "code": fcvtFpFixedCode, + "op_class": "FloatCvtOp" }, []) header_output += FpRegRegImmOpDeclare.subst(fcvtFpFixedIop); decoder_output += AA64FpRegRegImmOpConstructor.subst(fcvtFpFixedIop); exec_output += BasicExecute.subst(fcvtFpFixedIop); @@ -850,9 +851,9 @@ let {{ instName = "FJcvtFpSFixedDW" mnem = "fjcvtzs" - fcvtFpFixedIop = InstObjParams(mnem, instName, "FpRegRegOp", - { "code": fcvtFpFixedCode, - "op_class": "FloatCvtOp" }, []) + fcvtFpFixedIop = ArmInstObjParams(mnem, instName, "FpRegRegOp", + { "code": fcvtFpFixedCode, + "op_class": "FloatCvtOp" }, []) header_output += FpRegRegOpDeclare.subst(fcvtFpFixedIop); decoder_output += AA64FpRegRegOpConstructor.subst(fcvtFpFixedIop); exec_output += BasicExecute.subst(fcvtFpFixedIop); @@ -891,9 +892,9 @@ let {{ "D" if isDouble else "S", srcRegType) mnem = "%scvtf" %("s" if isSigned else "u") - fcvtFixedFpIop = InstObjParams(mnem, instName, "FpRegRegImmOp", - { "code": fcvtFixedFpCode, - "op_class": "FloatCvtOp" }, []) + fcvtFixedFpIop = ArmInstObjParams(mnem, instName, "FpRegRegImmOp", + { "code": fcvtFixedFpCode, + "op_class": "FloatCvtOp" }, []) fcvtFixedFpIop.snippets["code"] += zeroSveVecRegUpperPartCode % \ "AA64FpDest" header_output += FpRegRegImmOpDeclare.subst(fcvtFixedFpIop); @@ -940,9 +941,9 @@ let {{ AA64FpDestP3_uw = 0; ''' - iop = InstObjParams("fcsel", "FCSel%s" %("D" if isDouble else "S"), - "FpCondSelOp", { "code": code, - "op_class": "FloatCvtOp" }) + iop = ArmInstObjParams("fcsel", "FCSel%s" %("D" if isDouble else "S"), + "FpCondSelOp", { "code": code, + "op_class": "FloatCvtOp" }) iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" header_output += DataXCondSelDeclare.subst(iop) decoder_output += DataXCondSelConstructor.subst(iop) diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa index 48d533db0..9b3206527 100644 --- a/src/arch/arm/isa/insts/m5ops.isa +++ b/src/arch/arm/isa/insts/m5ops.isa @@ -43,20 +43,20 @@ let {{ if (!recognized) fault = std::make_shared(machInst, true); ''' - gem5OpIop = InstObjParams("gem5op", "Gem5Op64", "PredOp", - { "code": gem5OpCode + 'X0 = ret;', - "predicate_test": predicateTest }, - [ "IsNonSpeculative", "IsUnverifiable" ]); + gem5OpIop = ArmInstObjParams("gem5op", "Gem5Op64", "PredOp", + { "code": gem5OpCode + 'X0 = ret;', + "predicate_test": predicateTest }, + [ "IsNonSpeculative", "IsUnverifiable" ]); header_output += BasicDeclare.subst(gem5OpIop) decoder_output += BasicConstructor.subst(gem5OpIop) exec_output += PredOpExecute.subst(gem5OpIop) - gem5OpIop = InstObjParams("gem5op", "Gem5Op", "PredOp", - { "code": gem5OpCode + \ - 'R0 = bits(ret, 31, 0);\n' + \ - 'R1 = bits(ret, 63, 32);', - "predicate_test": predicateTest }, - [ "IsNonSpeculative", "IsUnverifiable" ]); + gem5OpIop = ArmInstObjParams("gem5op", "Gem5Op", "PredOp", + { "code": gem5OpCode + \ + 'R0 = bits(ret, 31, 0);\n' + \ + 'R1 = bits(ret, 63, 32);', + "predicate_test": predicateTest }, + [ "IsNonSpeculative", "IsUnverifiable" ]); header_output += BasicDeclare.subst(gem5OpIop) decoder_output += BasicConstructor.subst(gem5OpIop) exec_output += PredOpExecute.subst(gem5OpIop) diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index ad0f6778f..f9f6e724c 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -45,12 +45,11 @@ let {{ microLdrUopCode = "IWRa = cSwap(Mem_uw, ((CPSR)Cpsr).e);" - microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop', - 'MicroMemOp', - {'memacc_code': microLdrUopCode, - 'ea_code': 'EA = URb + (up ? imm : -imm);', - 'predicate_test': predicateTest}, - ['IsMicroop']) + microLdrUopIop = ArmInstObjParams('ldr_uop', 'MicroLdrUop', 'MicroMemOp', + { 'memacc_code' : microLdrUopCode, + 'ea_code' : 'EA = URb + (up ? imm : -imm);', + 'predicate_test' : predicateTest }, + ['IsMicroop']) microLdr2UopCode = ''' uint64_t data = Mem_ud; @@ -58,43 +57,41 @@ let {{ IWDest2 = cSwap((uint32_t) (data >> 32), ((CPSR)Cpsr).e); ''' - microLdr2UopIop = InstObjParams('ldr2_uop', 'MicroLdr2Uop', - 'MicroMemPairOp', - {'memacc_code': microLdr2UopCode, - 'ea_code': 'EA = URb + (up ? imm : -imm);', - 'predicate_test': predicateTest}, - ['IsMicroop']) + microLdr2UopIop = ArmInstObjParams('ldr2_uop', 'MicroLdr2Uop', + 'MicroMemPairOp', + { 'memacc_code' : microLdr2UopCode, + 'ea_code' : 'EA = URb + (up ? imm : -imm);', + 'predicate_test' : predicateTest }, + ['IsMicroop']) microLdrFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);" - microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop', - 'MicroMemOp', - {'memacc_code': microLdrFpUopCode, - 'ea_code': vfpEnabledCheckCode + - 'EA = URb + (up ? imm : -imm);', - 'predicate_test': predicateTest}, - ['IsMicroop']) + microLdrFpUopIop = ArmInstObjParams('ldrfp_uop', 'MicroLdrFpUop', + 'MicroMemOp', + { 'memacc_code' : microLdrFpUopCode, + 'ea_code' : vfpEnabledCheckCode + + 'EA = URb + (up ? imm : -imm);', + 'predicate_test': predicateTest }, + ['IsMicroop']) microLdrDBFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);" - microLdrDBFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDBFpUop', - 'MicroMemOp', - {'memacc_code': microLdrFpUopCode, - 'ea_code': vfpEnabledCheckCode + ''' - EA = URb + (up ? imm : -imm) + - (((CPSR)Cpsr).e ? 4 : 0); - ''', - 'predicate_test': predicateTest}, - ['IsMicroop']) + microLdrDBFpUopIop = ArmInstObjParams('ldrfp_uop', 'MicroLdrDBFpUop', + 'MicroMemOp', + { 'memacc_code' : microLdrFpUopCode, + 'ea_code' : vfpEnabledCheckCode + ''' + EA = URb + (up ? imm : -imm) + (((CPSR)Cpsr).e ? 4 : 0); + ''', + 'predicate_test' : predicateTest }, + ['IsMicroop']) microLdrDTFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);" - microLdrDTFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDTFpUop', - 'MicroMemOp', - {'memacc_code': microLdrFpUopCode, - 'ea_code': vfpEnabledCheckCode + ''' - EA = URb + (up ? imm : -imm) - - (((CPSR)Cpsr).e ? 4 : 0); - ''', - 'predicate_test': predicateTest}, - ['IsMicroop']) + microLdrDTFpUopIop = ArmInstObjParams('ldrfp_uop', 'MicroLdrDTFpUop', + 'MicroMemOp', + { 'memacc_code' : microLdrFpUopCode, + 'ea_code' : vfpEnabledCheckCode + ''' + EA = URb + (up ? imm : -imm) - (((CPSR)Cpsr).e ? 4 : 0); + ''', + 'predicate_test': predicateTest }, + ['IsMicroop']) microRetUopCode = ''' CPSR old_cpsr = Cpsr; @@ -114,58 +111,53 @@ let {{ SevMailbox = 1; ''' - microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop', - 'MicroMemOp', - {'memacc_code': - microRetUopCode % 'Mem_uw', - 'ea_code': - 'EA = URb + (up ? imm : -imm);', - 'predicate_test': condPredicateTest}, - ['IsMicroop','IsNonSpeculative', - 'IsSerializeAfter', 'IsSquashAfter']) + microLdrRetUopIop = ArmInstObjParams('ldr_ret_uop', 'MicroLdrRetUop', + 'MicroMemOp', + { 'memacc_code' : microRetUopCode % 'Mem_uw', + 'ea_code' : 'EA = URb + (up ? imm : -imm);', + 'predicate_test' : condPredicateTest }, + ['IsMicroop','IsNonSpeculative', + 'IsSerializeAfter', 'IsSquashAfter']) microStrUopCode = "Mem = cSwap(URa_uw, ((CPSR)Cpsr).e);" - microStrUopIop = InstObjParams('str_uop', 'MicroStrUop', - 'MicroMemOp', - {'memacc_code': microStrUopCode, - 'postacc_code': "", - 'ea_code': 'EA = URb + (up ? imm : -imm);', - 'predicate_test': predicateTest}, - ['IsMicroop']) + microStrUopIop = ArmInstObjParams('str_uop', 'MicroStrUop', 'MicroMemOp', + { 'memacc_code' : microStrUopCode, + 'postacc_code' : "", + 'ea_code' : 'EA = URb + (up ? imm : -imm);', + 'predicate_test' : predicateTest }, + ['IsMicroop']) microStrFpUopCode = "Mem = cSwap(Fa_uw, ((CPSR)Cpsr).e);" - microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop', - 'MicroMemOp', - {'memacc_code': microStrFpUopCode, - 'postacc_code': "", - 'ea_code': vfpEnabledCheckCode + - 'EA = URb + (up ? imm : -imm);', - 'predicate_test': predicateTest}, - ['IsMicroop']) + microStrFpUopIop = ArmInstObjParams('strfp_uop', 'MicroStrFpUop', + 'MicroMemOp', + { 'memacc_code' : microStrFpUopCode, + 'postacc_code' : "", + 'ea_code' : vfpEnabledCheckCode + + 'EA = URb + (up ? imm : -imm);', + 'predicate_test' : predicateTest }, + ['IsMicroop']) microStrDBFpUopCode = "Mem = cSwap(Fa_uw, ((CPSR)Cpsr).e);" - microStrDBFpUopIop = InstObjParams('strfp_uop', 'MicroStrDBFpUop', - 'MicroMemOp', - {'memacc_code': microStrFpUopCode, - 'postacc_code': "", - 'ea_code': vfpEnabledCheckCode + ''' - EA = URb + (up ? imm : -imm) + - (((CPSR)Cpsr).e ? 4 : 0); - ''', - 'predicate_test': predicateTest}, - ['IsMicroop']) + microStrDBFpUopIop = ArmInstObjParams('strfp_uop', 'MicroStrDBFpUop', + 'MicroMemOp', + { 'memacc_code' : microStrFpUopCode, + 'postacc_code' : "", + 'ea_code': vfpEnabledCheckCode + ''' + EA = URb + (up ? imm : -imm) + (((CPSR)Cpsr).e ? 4 : 0); + ''', + 'predicate_test' : predicateTest }, + ['IsMicroop']) microStrDTFpUopCode = "Mem = cSwap(Fa_uw, ((CPSR)Cpsr).e);" - microStrDTFpUopIop = InstObjParams('strfp_uop', 'MicroStrDTFpUop', - 'MicroMemOp', - {'memacc_code': microStrFpUopCode, - 'postacc_code': "", - 'ea_code': vfpEnabledCheckCode + ''' - EA = URb + (up ? imm : -imm) - - (((CPSR)Cpsr).e ? 4 : 0); - ''', - 'predicate_test': predicateTest}, - ['IsMicroop']) + microStrDTFpUopIop = ArmInstObjParams('strfp_uop', 'MicroStrDTFpUop', + 'MicroMemOp', + { 'memacc_code' : microStrFpUopCode, + 'postacc_code' : "", + 'ea_code' : vfpEnabledCheckCode + ''' + EA = URb + (up ? imm : -imm) - (((CPSR)Cpsr).e ? 4 : 0); + ''', + 'predicate_test' : predicateTest }, + ['IsMicroop']) header_output = decoder_output = exec_output = '' @@ -244,24 +236,22 @@ let {{ loadMemAccCode = convCode + regSetCode storeMemAccCode = regGetCode + convCode - loadIop = InstObjParams('ldrneon%(size)d_uop' % subst, - 'MicroLdrNeon%(size)dUop' % subst, - 'MicroNeonMemOp', - { 'mem_decl' : memDecl, - 'size' : size, - 'memacc_code' : loadMemAccCode, - 'ea_code' : simdEnabledCheckCode + eaCode, - 'predicate_test' : predicateTest }, - [ 'IsMicroop', 'IsLoad' ]) - storeIop = InstObjParams('strneon%(size)d_uop' % subst, - 'MicroStrNeon%(size)dUop' % subst, - 'MicroNeonMemOp', - { 'mem_decl' : memDecl, - 'size' : size, - 'memacc_code' : storeMemAccCode, - 'ea_code' : simdEnabledCheckCode + eaCode, - 'predicate_test' : predicateTest }, - [ 'IsMicroop', 'IsStore' ]) + loadIop = ArmInstObjParams('ldrneon%(size)d_uop' % subst, + 'MicroLdrNeon%(size)dUop' % subst, 'MicroNeonMemOp', + { 'mem_decl' : memDecl, + 'size' : size, + 'memacc_code' : loadMemAccCode, + 'ea_code' : simdEnabledCheckCode + eaCode, + 'predicate_test' : predicateTest }, + [ 'IsMicroop', 'IsLoad' ]) + storeIop = ArmInstObjParams('strneon%(size)d_uop' % subst, + 'MicroStrNeon%(size)dUop' % subst, 'MicroNeonMemOp', + { 'mem_decl' : memDecl, + 'size' : size, + 'memacc_code' : storeMemAccCode, + 'ea_code' : simdEnabledCheckCode + eaCode, + 'predicate_test' : predicateTest }, + [ 'IsMicroop', 'IsStore' ]) exec_output += NeonLoadExecute.subst(loadIop) + \ NeonLoadInitiateAcc.subst(loadIop) + \ @@ -343,12 +333,12 @@ let {{ "loadConv" : loadConv, "unloadConv" : unloadConv } microDeintNeonIop = \ - InstObjParams('deintneon%duop' % (dRegs * 2), - 'MicroDeintNeon%dUop' % (dRegs * 2), - 'MicroNeonMixOp', - { 'predicate_test': predicateTest, - 'code' : microDeintNeonCode }, - ['IsMicroop']) + ArmInstObjParams('deintneon%duop' % (dRegs * 2), + 'MicroDeintNeon%dUop' % (dRegs * 2), + 'MicroNeonMixOp', + { 'predicate_test': predicateTest, + 'code' : microDeintNeonCode }, + ['IsMicroop']) header_output += MicroNeonMixDeclare.subst(microDeintNeonIop) exec_output += MicroNeonMixExecute.subst(microDeintNeonIop) @@ -389,12 +379,12 @@ let {{ "loadConv" : loadConv, "unloadConv" : unloadConv } microInterNeonIop = \ - InstObjParams('interneon%duop' % (dRegs * 2), - 'MicroInterNeon%dUop' % (dRegs * 2), - 'MicroNeonMixOp', - { 'predicate_test': predicateTest, - 'code' : microInterNeonCode }, - ['IsMicroop']) + ArmInstObjParams('interneon%duop' % (dRegs * 2), + 'MicroInterNeon%dUop' % (dRegs * 2), + 'MicroNeonMixOp', + { 'predicate_test': predicateTest, + 'code' : microInterNeonCode }, + ['IsMicroop']) header_output += MicroNeonMixDeclare.subst(microInterNeonIop) exec_output += MicroNeonMixExecute.subst(microInterNeonIop) }}; @@ -461,14 +451,13 @@ let {{ ''' % { "sRegs" : sRegs, "dRegs" : dRegs, "loadRegs" : loadRegs, "unloadRegs" : unloadRegs } - microUnpackNeonIop = \ - InstObjParams('unpackneon%dto%duop' % (sRegs * 2, dRegs * 2), - 'MicroUnpackNeon%dto%dUop' % - (sRegs * 2, dRegs * 2), - 'MicroNeonMixLaneOp', - { 'predicate_test': predicateTest, - 'code' : microUnpackNeonCode }, - ['IsMicroop']) + microUnpackNeonIop = ArmInstObjParams( + 'unpackneon%dto%duop' % (sRegs * 2, dRegs * 2), + 'MicroUnpackNeon%dto%dUop' % (sRegs * 2, dRegs * 2), + 'MicroNeonMixLaneOp', + { 'predicate_test' : predicateTest, + 'code' : microUnpackNeonCode }, + ['IsMicroop']) header_output += MicroNeonMixLaneDeclare.subst(microUnpackNeonIop) exec_output += MicroNeonMixExecute.subst(microUnpackNeonIop) @@ -511,14 +500,13 @@ let {{ ''' % { "sRegs" : sRegs, "dRegs" : dRegs, "loadRegs" : loadRegs, "unloadRegs" : unloadRegs } - microUnpackAllNeonIop = \ - InstObjParams('unpackallneon%dto%duop' % (sRegs * 2, dRegs * 2), - 'MicroUnpackAllNeon%dto%dUop' % - (sRegs * 2, dRegs * 2), - 'MicroNeonMixOp', - { 'predicate_test': predicateTest, - 'code' : microUnpackAllNeonCode }, - ['IsMicroop']) + microUnpackAllNeonIop = ArmInstObjParams( + 'unpackallneon%dto%duop' % (sRegs * 2, dRegs * 2), + 'MicroUnpackAllNeon%dto%dUop' % (sRegs * 2, dRegs * 2), + 'MicroNeonMixOp', + { 'predicate_test' : predicateTest, + 'code' : microUnpackAllNeonCode }, + ['IsMicroop']) header_output += MicroNeonMixDeclare.subst(microUnpackAllNeonIop) exec_output += MicroNeonMixExecute.subst(microUnpackAllNeonIop) @@ -564,14 +552,13 @@ let {{ ''' % { "sRegs" : sRegs, "dRegs" : dRegs, "loadRegs" : loadRegs, "unloadRegs" : unloadRegs } - microPackNeonIop = \ - InstObjParams('packneon%dto%duop' % (sRegs * 2, dRegs * 2), - 'MicroPackNeon%dto%dUop' % - (sRegs * 2, dRegs * 2), - 'MicroNeonMixLaneOp', - { 'predicate_test': predicateTest, - 'code' : microPackNeonCode }, - ['IsMicroop']) + microPackNeonIop = ArmInstObjParams( + 'packneon%dto%duop' % (sRegs * 2, dRegs * 2), + 'MicroPackNeon%dto%dUop' % (sRegs * 2, dRegs * 2), + 'MicroNeonMixLaneOp', + { 'predicate_test': predicateTest, + 'code' : microPackNeonCode }, + ['IsMicroop']) header_output += MicroNeonMixLaneDeclare.subst(microPackNeonIop) exec_output += MicroNeonMixExecute.subst(microPackNeonIop) }}; @@ -597,23 +584,23 @@ let {{ // let {{ - microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop', - 'MicroIntImmOp', - {'code': 'URa = URb + imm;', - 'predicate_test': predicateTest}, - ['IsMicroop']) + microAddiUopIop = ArmInstObjParams('addi_uop', 'MicroAddiUop', + 'MicroIntImmOp', + {'code': 'URa = URb + imm;', + 'predicate_test': predicateTest}, + ['IsMicroop']) microAddUopCode = ''' URa = URb + shift_rm_imm(URc, shiftAmt, shiftType, OptShiftRmCondCodesC); ''' - microAddXiUopIop = InstObjParams('addxi_uop', 'MicroAddXiUop', - 'MicroIntImmXOp', - 'XURa = XURb + imm;', - ['IsMicroop']) + microAddXiUopIop = ArmInstObjParams('addxi_uop', 'MicroAddXiUop', + 'MicroIntImmXOp', + 'XURa = XURb + imm;', + ['IsMicroop']) - microAddXiSpAlignUopIop = InstObjParams('addxi_uop', 'MicroAddXiSpAlignUop', - 'MicroIntImmXOp', ''' + microAddXiSpAlignUopIop = ArmInstObjParams('addxi_uop', + 'MicroAddXiSpAlignUop', 'MicroIntImmXOp', ''' if (isSP((IntRegIndex) urb) && bits(XURb, 3, 0) && SPAlignmentCheckEnabled(xc->tcBase())) { return std::make_shared(); @@ -621,50 +608,47 @@ let {{ XURa = XURb + imm; ''', ['IsMicroop']) - microAddXERegUopIop = InstObjParams('addxr_uop', 'MicroAddXERegUop', - 'MicroIntRegXOp', - 'XURa = XURb + ' + \ - 'extendReg64(XURc, type, shiftAmt, 64);', - ['IsMicroop']) + microAddXERegUopIop = ArmInstObjParams('addxr_uop', + 'MicroAddXERegUop', 'MicroIntRegXOp', + 'XURa = XURb + extendReg64(XURc, type, shiftAmt, 64);', + ['IsMicroop']) - microAddUopIop = InstObjParams('add_uop', 'MicroAddUop', - 'MicroIntRegOp', - {'code': microAddUopCode, - 'predicate_test': pickPredicate(microAddUopCode)}, - ['IsMicroop']) + microAddUopIop = ArmInstObjParams('add_uop', 'MicroAddUop', + 'MicroIntRegOp', + { 'code' : microAddUopCode, + 'predicate_test': pickPredicate(microAddUopCode)}, + ['IsMicroop']) - microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop', - 'MicroIntImmOp', - {'code': 'URa = URb - imm;', - 'predicate_test': predicateTest}, - ['IsMicroop']) + microSubiUopIop = ArmInstObjParams('subi_uop', 'MicroSubiUop', + 'MicroIntImmOp', + { 'code' : 'URa = URb - imm;', + 'predicate_test' : predicateTest}, + ['IsMicroop']) - microSubXiUopIop = InstObjParams('subxi_uop', 'MicroSubXiUop', - 'MicroIntImmXOp', - 'XURa = XURb - imm;', - ['IsMicroop']) + microSubXiUopIop = ArmInstObjParams('subxi_uop', 'MicroSubXiUop', + 'MicroIntImmXOp', 'XURa = XURb - imm;', ['IsMicroop']) microSubUopCode = ''' URa = URb - shift_rm_imm(URc, shiftAmt, shiftType, OptShiftRmCondCodesC); ''' - microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop', - 'MicroIntRegOp', - {'code': microSubUopCode, - 'predicate_test': pickPredicate(microSubUopCode)}, - ['IsMicroop']) - - microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov', - 'MicroIntMov', - {'code': 'IWRa = URb;', - 'predicate_test': predicateTest}, - ['IsMicroop']) - - microUopRegMovRetIop = InstObjParams('movret_uop', 'MicroUopRegMovRet', - 'MicroIntMov', - {'code': microRetUopCode % 'URb', - 'predicate_test': predicateTest}, - ['IsMicroop', 'IsNonSpeculative', - 'IsSerializeAfter', 'IsSquashAfter']) + microSubUopIop = ArmInstObjParams('sub_uop', 'MicroSubUop', + 'MicroIntRegOp', + { 'code' : microSubUopCode, + 'predicate_test' : pickPredicate(microSubUopCode) }, + ['IsMicroop']) + + microUopRegMovIop = ArmInstObjParams('uopReg_uop', 'MicroUopRegMov', + 'MicroIntMov', + { 'code' : 'IWRa = URb;', + 'predicate_test' : predicateTest }, + ['IsMicroop']) + + microUopRegMovRetIop = ArmInstObjParams('movret_uop', 'MicroUopRegMovRet', + 'MicroIntMov', + { 'code': microRetUopCode % 'URb', + 'predicate_test': predicateTest}, + [ 'IsMicroop', 'IsNonSpeculative', + 'IsSerializeAfter', 'IsSquashAfter']) setPCCPSRDecl = ''' CPSR cpsrOrCondCodes = URc; @@ -684,11 +668,11 @@ let {{ CondCodesGE = new_cpsr.ge; ''' - microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR', - 'MicroSetPCCPSR', - {'code': setPCCPSRDecl, - 'predicate_test': predicateTest}, - ['IsMicroop', 'IsSerializeAfter']) + microUopSetPCCPSRIop = ArmInstObjParams('uopSet_uop', 'MicroUopSetPCCPSR', + 'MicroSetPCCPSR', + { 'code' : setPCCPSRDecl, + 'predicate_test' : predicateTest }, + ['IsMicroop', 'IsSerializeAfter']) header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \ MicroIntImmDeclare.subst(microAddXiUopIop) + \ @@ -729,46 +713,49 @@ let {{ }}; let {{ - iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", []) + iop = ArmInstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", []) header_output = MacroMemDeclare.subst(iop) decoder_output = MacroMemConstructor.subst(iop) - iop = InstObjParams("ldpstp", "LdpStp", 'PairMemOp', "", []) + iop = ArmInstObjParams("ldpstp", "LdpStp", 'PairMemOp', "", []) header_output += PairMemDeclare.subst(iop) decoder_output += PairMemConstructor.subst(iop) - iopImm = InstObjParams("bigfpmemimm", "BigFpMemImm", "BigFpMemImmOp", "") - iopPre = InstObjParams("bigfpmempre", "BigFpMemPre", "BigFpMemPreOp", "") - iopPost = InstObjParams("bigfpmempost", "BigFpMemPost", "BigFpMemPostOp", "") + iopImm = ArmInstObjParams( + "bigfpmemimm", "BigFpMemImm", "BigFpMemImmOp", "") + iopPre = ArmInstObjParams( + "bigfpmempre", "BigFpMemPre", "BigFpMemPreOp", "") + iopPost = ArmInstObjParams( + "bigfpmempost", "BigFpMemPost", "BigFpMemPostOp", "") for iop in (iopImm, iopPre, iopPost): header_output += BigFpMemImmDeclare.subst(iop) decoder_output += BigFpMemImmConstructor.subst(iop) - iop = InstObjParams("bigfpmemreg", "BigFpMemReg", "BigFpMemRegOp", "") + iop = ArmInstObjParams("bigfpmemreg", "BigFpMemReg", "BigFpMemRegOp", "") header_output += BigFpMemRegDeclare.subst(iop) decoder_output += BigFpMemRegConstructor.subst(iop) - iop = InstObjParams("bigfpmemlit", "BigFpMemLit", "BigFpMemLitOp", "") + iop = ArmInstObjParams("bigfpmemlit", "BigFpMemLit", "BigFpMemLitOp", "") header_output += BigFpMemLitDeclare.subst(iop) decoder_output += BigFpMemLitConstructor.subst(iop) - iop = InstObjParams("vldmult", "VldMult", 'VldMultOp', "", []) + iop = ArmInstObjParams("vldmult", "VldMult", 'VldMultOp', "", []) header_output += VMemMultDeclare.subst(iop) decoder_output += VMemMultConstructor.subst(iop) - iop = InstObjParams("vldsingle", "VldSingle", 'VldSingleOp', "", []) + iop = ArmInstObjParams("vldsingle", "VldSingle", 'VldSingleOp', "", []) header_output += VMemSingleDeclare.subst(iop) decoder_output += VMemSingleConstructor.subst(iop) - iop = InstObjParams("vstmult", "VstMult", 'VstMultOp', "", []) + iop = ArmInstObjParams("vstmult", "VstMult", 'VstMultOp', "", []) header_output += VMemMultDeclare.subst(iop) decoder_output += VMemMultConstructor.subst(iop) - iop = InstObjParams("vstsingle", "VstSingle", 'VstSingleOp', "", []) + iop = ArmInstObjParams("vstsingle", "VstSingle", 'VstSingleOp', "", []) header_output += VMemSingleDeclare.subst(iop) decoder_output += VMemSingleConstructor.subst(iop) - vfpIop = InstObjParams("vldmstm", "VLdmStm", 'MacroVFPMemOp', "", []) + vfpIop = ArmInstObjParams("vldmstm", "VLdmStm", 'MacroVFPMemOp', "", []) header_output += MacroVFPMemDeclare.subst(vfpIop) decoder_output += MacroVFPMemConstructor.subst(vfpIop) }}; diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa index 685f764a6..760a354bf 100644 --- a/src/arch/arm/isa/insts/mem.isa +++ b/src/arch/arm/isa/insts/mem.isa @@ -107,8 +107,8 @@ let {{ if 'memacc_epilog_code' in codeBlobsCopy: del codeBlobsCopy['memacc_epilog_code'] - iop = InstObjParams(name, Name, base, - codeBlobsCopy, instFlagsCopy) + iop = ArmInstObjParams(name, Name, base, + codeBlobsCopy, instFlagsCopy) if 'memacc_epilog_code' in codeBlobs: iop.snippets['memacc_code'] += codeBlobs['memacc_epilog_code'] header_output = self.declareTemplate.subst(iop) @@ -118,16 +118,16 @@ let {{ self.completeAccTemplate.subst(iop) if wbDecl is not None or pcDecl is not None: - iop = InstObjParams(name, macroName, base, - { "wb_decl" : wbDecl, - "pc_decl" : pcDecl, - "acc_name" : Name, - "use_uops" : use_uops, - "use_pc" : use_pc, - "use_wb" : use_wb, - "fa_code" : '', - "is_ras_pop" : is_ras_pop }, - ['IsMacroop']) + iop = ArmInstObjParams(name, macroName, base, + { "wb_decl" : wbDecl, + "pc_decl" : pcDecl, + "acc_name" : Name, + "use_uops" : use_uops, + "use_pc" : use_pc, + "use_wb" : use_wb, + "fa_code" : '', + "is_ras_pop" : is_ras_pop }, + ['IsMacroop']) header_output += self.declareTemplate.subst(iop) decoder_output += self.constructTemplate.subst(iop) exec_output += PanicExecute.subst(iop) + \ diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 17c30ff69..176e031b9 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -53,13 +53,13 @@ let {{ } ''' - svcIop = InstObjParams("svc", "Svc", "ImmOp", - { "code": svcCode, - "predicate_test": predicateTest, - "thumb_semihost": '0xAB', - "arm_semihost": '0x123456' }, - ["IsSyscall", "IsNonSpeculative", - "IsSerializeAfter"]) + svcIop = ArmInstObjParams("svc", "Svc", "ImmOp", + { "code": svcCode, + "predicate_test": predicateTest, + "thumb_semihost": '0xAB', + "arm_semihost": '0x123456' }, + ["IsSyscall", "IsNonSpeculative", + "IsSerializeAfter"]) header_output = ImmOpDeclare.subst(svcIop) decoder_output = SemihostConstructor.subst(svcIop) exec_output = PredOpExecute.subst(svcIop) @@ -79,12 +79,12 @@ let {{ } ''' - hltIop = InstObjParams("hlt", "Hlt", "ImmOp", - { "code": hltCode, - "predicate_test": predicateTest, - "thumb_semihost": '0x3C', - "arm_semihost": '0xF000' }, - ["IsNonSpeculative", "IsSerializeAfter"]) + hltIop = ArmInstObjParams("hlt", "Hlt", "ImmOp", + { "code": hltCode, + "predicate_test": predicateTest, + "thumb_semihost": '0x3C', + "arm_semihost": '0xF000' }, + ["IsNonSpeculative", "IsSerializeAfter"]) header_output += ImmOpDeclare.subst(hltIop) decoder_output += SemihostConstructor.subst(hltIop) exec_output += PredOpExecute.subst(hltIop) @@ -110,10 +110,10 @@ let {{ } ''' - smcIop = InstObjParams("smc", "Smc", "PredOp", - { "code": smcCode, - "predicate_test": predicateTest }, - ["IsNonSpeculative", "IsSerializeAfter"]) + smcIop = ArmInstObjParams("smc", "Smc", "PredOp", + { "code": smcCode, + "predicate_test": predicateTest }, + ["IsNonSpeculative", "IsSerializeAfter"]) header_output += BasicDeclare.subst(smcIop) decoder_output += BasicConstructor.subst(smcIop) exec_output += PredOpExecute.subst(smcIop) @@ -134,10 +134,10 @@ let {{ } ''' - hvcIop = InstObjParams("hvc", "Hvc", "ImmOp", - { "code": hvcCode, - "predicate_test": predicateTest }, - ["IsNonSpeculative", "IsSerializeAfter"]) + hvcIop = ArmInstObjParams("hvc", "Hvc", "ImmOp", + { "code": hvcCode, + "predicate_test": predicateTest }, + ["IsNonSpeculative", "IsSerializeAfter"]) header_output += ImmOpDeclare.subst(hvcIop) decoder_output += ImmOpConstructor.subst(hvcIop) exec_output += PredOpExecute.subst(hvcIop) @@ -172,11 +172,11 @@ let {{ NPC = (old_cpsr.mode == MODE_HYP) ? ElrHyp : LR; ''' - eretIop = InstObjParams("eret", "Eret", "PredOp", - { "code": eretCode, - "predicate_test": predicateTest }, - ["IsNonSpeculative", "IsSerializeAfter", - "IsSquashAfter"]) + eretIop = ArmInstObjParams("eret", "Eret", "PredOp", + { "code": eretCode, + "predicate_test": predicateTest }, + ["IsNonSpeculative", "IsSerializeAfter", + "IsSquashAfter"]) header_output += BasicDeclare.subst(eretIop) decoder_output += BasicConstructor.subst(eretIop) exec_output += PredOpExecute.subst(eretIop) @@ -209,9 +209,9 @@ let {{ instCode = implCode % data - crcIop = InstObjParams(mnem, mnem.capitalize(), "RegRegRegOp", - { "code": instCode, - "predicate_test": predicateTest }, []) + crcIop = ArmInstObjParams(mnem, mnem.capitalize(), "RegRegRegOp", + { "code": instCode, + "predicate_test": predicateTest }, []) header_output += RegRegRegOpDeclare.subst(crcIop) decoder_output += RegRegRegOpConstructor.subst(crcIop) exec_output += PredOpExecute.subst(crcIop) @@ -238,19 +238,19 @@ let {{ Dest = cpsr & (cpsr.mode == MODE_USER ? ApsrMask : CpsrMask); ''' - mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", - { "code": mrsCpsrCode, - "predicate_test": condPredicateTest }, - ["IsSerializeBefore"]) + mrsCpsrIop = ArmInstObjParams("mrs", "MrsCpsr", "MrsOp", + { "code": mrsCpsrCode, + "predicate_test": condPredicateTest }, + ["IsSerializeBefore"]) header_output += MrsDeclare.subst(mrsCpsrIop) decoder_output += MrsConstructor.subst(mrsCpsrIop) exec_output += PredOpExecute.subst(mrsCpsrIop) mrsSpsrCode = "Dest = Spsr" - mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp", - { "code": mrsSpsrCode, - "predicate_test": predicateTest }, - ["IsSerializeBefore"]) + mrsSpsrIop = ArmInstObjParams("mrs", "MrsSpsr", "MrsOp", + { "code": mrsSpsrCode, + "predicate_test": predicateTest }, + ["IsSerializeBefore"]) header_output += MrsDeclare.subst(mrsSpsrIop) decoder_output += MrsConstructor.subst(mrsSpsrIop) exec_output += PredOpExecute.subst(mrsSpsrIop) @@ -270,10 +270,10 @@ let {{ mnemonic); } ''' - mrsBankedRegIop = InstObjParams("mrs", "MrsBankedReg", "MrsOp", - { "code": mrsBankedRegCode, - "predicate_test": predicateTest }, - ["IsSerializeBefore"]) + mrsBankedRegIop = ArmInstObjParams("mrs", "MrsBankedReg", "MrsOp", + { "code": mrsBankedRegCode, + "predicate_test": predicateTest }, + ["IsSerializeBefore"]) header_output += MrsBankedRegDeclare.subst(mrsBankedRegIop) decoder_output += MrsBankedRegConstructor.subst(mrsBankedRegIop) exec_output += PredOpExecute.subst(mrsBankedRegIop) @@ -302,10 +302,11 @@ let {{ mnemonic); } ''' - msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp", - { "code": msrBankedRegCode, - "predicate_test": predicateTest }, - ["IsSerializeAfter", "IsNonSpeculative"]) + msrBankedRegIop = ArmInstObjParams("msr", "MsrBankedReg", "MsrRegOp", + { "code": msrBankedRegCode, + "predicate_test": predicateTest }, + ["IsSerializeAfter", + "IsNonSpeculative"]) header_output += MsrBankedRegDeclare.subst(msrBankedRegIop) decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop) exec_output += PredOpExecute.subst(msrBankedRegIop) @@ -327,19 +328,19 @@ let {{ CondCodesV = new_cpsr.v; CondCodesGE = new_cpsr.ge; ''' - msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", - { "code": msrCpsrRegCode, - "predicate_test": condPredicateTest }, - ["IsSerializeAfter","IsNonSpeculative"]) + msrCpsrRegIop = ArmInstObjParams("msr", "MsrCpsrReg", "MsrRegOp", + { "code": msrCpsrRegCode, + "predicate_test": condPredicateTest }, + ["IsSerializeAfter","IsNonSpeculative"]) header_output += MsrRegDeclare.subst(msrCpsrRegIop) decoder_output += MsrRegConstructor.subst(msrCpsrRegIop) exec_output += PredOpExecute.subst(msrCpsrRegIop) msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);" - msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp", - { "code": msrSpsrRegCode, - "predicate_test": predicateTest }, - ["IsSerializeAfter","IsNonSpeculative"]) + msrSpsrRegIop = ArmInstObjParams("msr", "MsrSpsrReg", "MsrRegOp", + { "code": msrSpsrRegCode, + "predicate_test": predicateTest }, + ["IsSerializeAfter","IsNonSpeculative"]) header_output += MsrRegDeclare.subst(msrSpsrRegIop) decoder_output += MsrRegConstructor.subst(msrSpsrRegIop) exec_output += PredOpExecute.subst(msrSpsrRegIop) @@ -360,19 +361,19 @@ let {{ CondCodesV = new_cpsr.v; CondCodesGE = new_cpsr.ge; ''' - msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", - { "code": msrCpsrImmCode, - "predicate_test": condPredicateTest }, - ["IsSerializeAfter","IsNonSpeculative"]) + msrCpsrImmIop = ArmInstObjParams("msr", "MsrCpsrImm", "MsrImmOp", + { "code": msrCpsrImmCode, + "predicate_test": condPredicateTest }, + ["IsSerializeAfter","IsNonSpeculative"]) header_output += MsrImmDeclare.subst(msrCpsrImmIop) decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) exec_output += PredOpExecute.subst(msrCpsrImmIop) msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);" - msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp", - { "code": msrSpsrImmCode, - "predicate_test": predicateTest }, - ["IsSerializeAfter","IsNonSpeculative"]) + msrSpsrImmIop = ArmInstObjParams("msr", "MsrSpsrImm", "MsrImmOp", + { "code": msrSpsrImmCode, + "predicate_test": predicateTest }, + ["IsSerializeAfter","IsNonSpeculative"]) header_output += MsrImmDeclare.subst(msrSpsrImmIop) decoder_output += MsrImmConstructor.subst(msrSpsrImmIop) exec_output += PredOpExecute.subst(msrSpsrImmIop) @@ -381,9 +382,9 @@ let {{ uint32_t val = Op1; Dest = swap_byte(val); ''' - revIop = InstObjParams("rev", "Rev", "RegRegOp", - { "code": revCode, - "predicate_test": predicateTest }, []) + revIop = ArmInstObjParams("rev", "Rev", "RegRegOp", + { "code": revCode, + "predicate_test": predicateTest }, []) header_output += RegRegOpDeclare.subst(revIop) decoder_output += RegRegOpConstructor.subst(revIop) exec_output += PredOpExecute.subst(revIop) @@ -395,9 +396,9 @@ let {{ (bits(val, 31, 24) << 16) | (bits(val, 23, 16) << 24); ''' - rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp", - { "code": rev16Code, - "predicate_test": predicateTest }, []) + rev16Iop = ArmInstObjParams("rev16", "Rev16", "RegRegOp", + { "code": rev16Code, + "predicate_test": predicateTest }, []) header_output += RegRegOpDeclare.subst(rev16Iop) decoder_output += RegRegOpConstructor.subst(rev16Iop) exec_output += PredOpExecute.subst(rev16Iop) @@ -406,9 +407,9 @@ let {{ uint16_t val = Op1; Dest = sext<16>(swap_byte(val)); ''' - revshIop = InstObjParams("revsh", "Revsh", "RegRegOp", - { "code": revshCode, - "predicate_test": predicateTest }, []) + revshIop = ArmInstObjParams("revsh", "Revsh", "RegRegOp", + { "code": revshCode, + "predicate_test": predicateTest }, []) header_output += RegRegOpDeclare.subst(revshIop) decoder_output += RegRegOpConstructor.subst(revshIop) exec_output += PredOpExecute.subst(revshIop) @@ -416,9 +417,9 @@ let {{ rbitCode = ''' Dest = reverseBits(Op1); ''' - rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp", - { "code": rbitCode, - "predicate_test": predicateTest }, []) + rbitIop = ArmInstObjParams("rbit", "Rbit", "RegRegOp", + { "code": rbitCode, + "predicate_test": predicateTest }, []) header_output += RegRegOpDeclare.subst(rbitIop) decoder_output += RegRegOpConstructor.subst(rbitIop) exec_output += PredOpExecute.subst(rbitIop) @@ -426,9 +427,9 @@ let {{ clzCode = ''' Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1)); ''' - clzIop = InstObjParams("clz", "Clz", "RegRegOp", - { "code": clzCode, - "predicate_test": predicateTest }, []) + clzIop = ArmInstObjParams("clz", "Clz", "RegRegOp", + { "code": clzCode, + "predicate_test": predicateTest }, []) header_output += RegRegOpDeclare.subst(clzIop) decoder_output += RegRegOpConstructor.subst(clzIop) exec_output += PredOpExecute.subst(clzIop) @@ -440,9 +441,10 @@ let {{ CpsrQ = 1 << 27; Dest = res; ''' - ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", - { "code": ssatCode, - "predicate_test": pickPredicate(ssatCode) }, []) + ssatIop = ArmInstObjParams("ssat", "Ssat", "RegImmRegShiftOp", + { "code": ssatCode, + "predicate_test": pickPredicate(ssatCode) }, + []) header_output += RegImmRegShiftOpDeclare.subst(ssatIop) decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop) exec_output += PredOpExecute.subst(ssatIop) @@ -454,9 +456,10 @@ let {{ CpsrQ = 1 << 27; Dest = res; ''' - usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", - { "code": usatCode, - "predicate_test": pickPredicate(usatCode) }, []) + usatIop = ArmInstObjParams("usat", "Usat", "RegImmRegShiftOp", + { "code": usatCode, + "predicate_test": pickPredicate(usatCode) }, + []) header_output += RegImmRegShiftOpDeclare.subst(usatIop) decoder_output += RegImmRegShiftOpConstructor.subst(usatIop) exec_output += PredOpExecute.subst(usatIop) @@ -474,9 +477,10 @@ let {{ replaceBits(resTemp, 31, 16, res); Dest = resTemp; ''' - ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp", - { "code": ssat16Code, - "predicate_test": pickPredicate(ssat16Code) }, []) + ssat16Iop = ArmInstObjParams("ssat16", "Ssat16", "RegImmRegOp", + { "code": ssat16Code, + "predicate_test": + pickPredicate(ssat16Code) }, []) header_output += RegImmRegOpDeclare.subst(ssat16Iop) decoder_output += RegImmRegOpConstructor.subst(ssat16Iop) exec_output += PredOpExecute.subst(ssat16Iop) @@ -494,28 +498,29 @@ let {{ replaceBits(resTemp, 31, 16, res); Dest = resTemp; ''' - usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp", - { "code": usat16Code, - "predicate_test": pickPredicate(usat16Code) }, []) + usat16Iop = ArmInstObjParams("usat16", "Usat16", "RegImmRegOp", + { "code": usat16Code, + "predicate_test": + pickPredicate(usat16Code) }, []) header_output += RegImmRegOpDeclare.subst(usat16Iop) decoder_output += RegImmRegOpConstructor.subst(usat16Iop) exec_output += PredOpExecute.subst(usat16Iop) - sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp", - { "code": - "Dest = sext<8>((uint8_t)(Op1_ud >> imm));", - "predicate_test": predicateTest }, []) + sxtbIop = ArmInstObjParams("sxtb", "Sxtb", "RegImmRegOp", + { "code": + "Dest = sext<8>((uint8_t)(Op1_ud >> imm));", + "predicate_test": predicateTest }, []) header_output += RegImmRegOpDeclare.subst(sxtbIop) decoder_output += RegImmRegOpConstructor.subst(sxtbIop) exec_output += PredOpExecute.subst(sxtbIop) - sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", - { "code": - ''' - Dest = sext<8>((uint8_t)(Op2_ud >> imm)) + - Op1; - ''', - "predicate_test": predicateTest }, []) + sxtabIop = ArmInstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", + { "code": + ''' + Dest = sext<8>((uint8_t)(Op2_ud >> imm)) + + Op1; + ''', + "predicate_test": predicateTest }, []) header_output += RegRegRegImmOpDeclare.subst(sxtabIop) decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop) exec_output += PredOpExecute.subst(sxtabIop) @@ -527,9 +532,9 @@ let {{ sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); Dest = resTemp; ''' - sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp", - { "code": sxtb16Code, - "predicate_test": predicateTest }, []) + sxtb16Iop = ArmInstObjParams("sxtb16", "Sxtb16", "RegImmRegOp", + { "code": sxtb16Code, + "predicate_test": predicateTest }, []) header_output += RegImmRegOpDeclare.subst(sxtb16Iop) decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop) exec_output += PredOpExecute.subst(sxtb16Iop) @@ -543,9 +548,9 @@ let {{ bits(Op1, 31, 16)); Dest = resTemp; ''' - sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp", - { "code": sxtab16Code, - "predicate_test": predicateTest }, []) + sxtab16Iop = ArmInstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp", + { "code": sxtab16Code, + "predicate_test": predicateTest }, []) header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop) decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop) exec_output += PredOpExecute.subst(sxtab16Iop) @@ -555,9 +560,9 @@ let {{ rotated = (rotated | (rotated << 32)) >> imm; Dest = sext<16>((uint16_t)rotated); ''' - sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp", - { "code": sxthCode, - "predicate_test": predicateTest }, []) + sxthIop = ArmInstObjParams("sxth", "Sxth", "RegImmRegOp", + { "code": sxthCode, + "predicate_test": predicateTest }, []) header_output += RegImmRegOpDeclare.subst(sxthIop) decoder_output += RegImmRegOpConstructor.subst(sxthIop) exec_output += PredOpExecute.subst(sxthIop) @@ -567,24 +572,24 @@ let {{ rotated = (rotated | (rotated << 32)) >> imm; Dest = sext<16>((uint16_t)rotated) + Op1; ''' - sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp", - { "code": sxtahCode, - "predicate_test": predicateTest }, []) + sxtahIop = ArmInstObjParams("sxtah", "Sxtah", "RegRegRegImmOp", + { "code": sxtahCode, + "predicate_test": predicateTest }, []) header_output += RegRegRegImmOpDeclare.subst(sxtahIop) decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop) exec_output += PredOpExecute.subst(sxtahIop) - uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp", - { "code": "Dest = (uint8_t)(Op1_ud >> imm);", - "predicate_test": predicateTest }, []) + uxtbIop = ArmInstObjParams("uxtb", "Uxtb", "RegImmRegOp", + { "code": "Dest = (uint8_t)(Op1_ud >> imm);", + "predicate_test": predicateTest }, []) header_output += RegImmRegOpDeclare.subst(uxtbIop) decoder_output += RegImmRegOpConstructor.subst(uxtbIop) exec_output += PredOpExecute.subst(uxtbIop) - uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", - { "code": - "Dest = (uint8_t)(Op2_ud >> imm) + Op1;", - "predicate_test": predicateTest }, []) + uxtabIop = ArmInstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", + { "code": + "Dest = (uint8_t)(Op2_ud >> imm) + Op1;", + "predicate_test": predicateTest }, []) header_output += RegRegRegImmOpDeclare.subst(uxtabIop) decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop) exec_output += PredOpExecute.subst(uxtabIop) @@ -596,9 +601,9 @@ let {{ (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); Dest = resTemp; ''' - uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp", - { "code": uxtb16Code, - "predicate_test": predicateTest }, []) + uxtb16Iop = ArmInstObjParams("uxtb16", "Uxtb16", "RegImmRegOp", + { "code": uxtb16Code, + "predicate_test": predicateTest }, []) header_output += RegImmRegOpDeclare.subst(uxtb16Iop) decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop) exec_output += PredOpExecute.subst(uxtb16Iop) @@ -612,9 +617,9 @@ let {{ bits(Op1, 31, 16)); Dest = resTemp; ''' - uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp", - { "code": uxtab16Code, - "predicate_test": predicateTest }, []) + uxtab16Iop = ArmInstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp", + { "code": uxtab16Code, + "predicate_test": predicateTest }, []) header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop) decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop) exec_output += PredOpExecute.subst(uxtab16Iop) @@ -624,9 +629,9 @@ let {{ rotated = (rotated | (rotated << 32)) >> imm; Dest = (uint16_t)rotated; ''' - uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp", - { "code": uxthCode, - "predicate_test": predicateTest }, []) + uxthIop = ArmInstObjParams("uxth", "Uxth", "RegImmRegOp", + { "code": uxthCode, + "predicate_test": predicateTest }, []) header_output += RegImmRegOpDeclare.subst(uxthIop) decoder_output += RegImmRegOpConstructor.subst(uxthIop) exec_output += PredOpExecute.subst(uxthIop) @@ -636,9 +641,9 @@ let {{ rotated = (rotated | (rotated << 32)) >> imm; Dest = (uint16_t)rotated + Op1; ''' - uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp", - { "code": uxtahCode, - "predicate_test": predicateTest }, []) + uxtahIop = ArmInstObjParams("uxtah", "Uxtah", "RegRegRegImmOp", + { "code": uxtahCode, + "predicate_test": predicateTest }, []) header_output += RegRegRegImmOpDeclare.subst(uxtahIop) decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop) exec_output += PredOpExecute.subst(uxtahIop) @@ -654,9 +659,9 @@ let {{ } Dest = resTemp; ''' - selIop = InstObjParams("sel", "Sel", "RegRegRegOp", - { "code": selCode, - "predicate_test": predicateTest }, []) + selIop = ArmInstObjParams("sel", "Sel", "RegRegRegOp", + { "code": selCode, + "predicate_test": predicateTest }, []) header_output += RegRegRegOpDeclare.subst(selIop) decoder_output += RegRegRegOpConstructor.subst(selIop) exec_output += PredOpExecute.subst(selIop) @@ -672,9 +677,9 @@ let {{ } Dest = resTemp; ''' - usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp", - { "code": usad8Code, - "predicate_test": predicateTest }, []) + usad8Iop = ArmInstObjParams("usad8", "Usad8", "RegRegRegOp", + { "code": usad8Code, + "predicate_test": predicateTest }, []) header_output += RegRegRegOpDeclare.subst(usad8Iop) decoder_output += RegRegRegOpConstructor.subst(usad8Iop) exec_output += PredOpExecute.subst(usad8Iop) @@ -690,9 +695,9 @@ let {{ } Dest = Op3 + resTemp; ''' - usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp", - { "code": usada8Code, - "predicate_test": predicateTest }, []) + usada8Iop = ArmInstObjParams("usada8", "Usada8", "RegRegRegRegOp", + { "code": usada8Code, + "predicate_test": predicateTest }, []) header_output += RegRegRegRegOpDeclare.subst(usada8Iop) decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) exec_output += PredOpExecute.subst(usada8Iop) @@ -706,17 +711,17 @@ let {{ return softwareBreakpoint32(xc, imm16); ''' - bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode) + bkptIop = ArmInstObjParams("bkpt", "BkptInst", "PredOp", bkptCode) header_output += BasicDeclare.subst(bkptIop) decoder_output += BasicConstructor.subst(bkptIop) exec_output += BasicExecute.subst(bkptIop) - nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", ['IsNop']) + nopIop = ArmInstObjParams("nop", "NopInst", "ArmStaticInst", "", ['IsNop']) header_output += BasicDeclare.subst(nopIop) decoder_output += BasicConstructor64.subst(nopIop) exec_output += BasicExecute.subst(nopIop) - yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \ + yieldIop = ArmInstObjParams("yield", "YieldInst", "PredOp", \ { "code" : "", "predicate_test" : predicateTest }) header_output += BasicDeclare.subst(yieldIop) decoder_output += BasicConstructor.subst(yieldIop) @@ -749,7 +754,7 @@ let {{ // and SEV interrupts SevMailbox = 1; ''' - wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ + wfeIop = ArmInstObjParams("wfe", "WfeInst", "PredOp", \ { "code" : wfeCode, "pred_fixup" : wfePredFixUpCode, "predicate_test" : predicateTest }, @@ -788,7 +793,7 @@ let {{ } tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); ''' - wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ + wfiIop = ArmInstObjParams("wfi", "WfiInst", "PredOp", \ { "code" : wfiCode, "predicate_test" : predicateTest }, ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter", "IsUnverifiable"]) @@ -808,7 +813,7 @@ let {{ sendEvent(oc); } ''' - sevIop = InstObjParams("sev", "SevInst", "PredOp", \ + sevIop = ArmInstObjParams("sev", "SevInst", "PredOp", \ { "code" : sevCode, "predicate_test" : predicateTest }, ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"]) header_output += BasicDeclare.subst(sevIop) @@ -818,14 +823,14 @@ let {{ sevlCode = ''' SevMailbox = 1; ''' - sevlIop = InstObjParams("sevl", "SevlInst", "PredOp", \ + sevlIop = ArmInstObjParams("sevl", "SevlInst", "PredOp", \ { "code" : sevlCode, "predicate_test" : predicateTest }, ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"]) header_output += BasicDeclare.subst(sevlIop) decoder_output += BasicConstructor.subst(sevlIop) exec_output += BasicExecute.subst(sevlIop) - itIop = InstObjParams("it", "ItInst", "PredOp", \ + itIop = ArmInstObjParams("it", "ItInst", "PredOp", \ { "code" : ";", "predicate_test" : predicateTest }, []) header_output += BasicDeclare.subst(itIop) @@ -834,9 +839,9 @@ let {{ unknownCode = ''' return std::make_shared(machInst, true); ''' - unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ - { "code": unknownCode, - "predicate_test": predicateTest }) + unknownIop = ArmInstObjParams("unknown", "Unknown", "UnknownOp", \ + { "code": unknownCode, + "predicate_test": predicateTest }) header_output += BasicDeclare.subst(unknownIop) decoder_output += BasicConstructor.subst(unknownIop) exec_output += PredOpExecute.subst(unknownIop) @@ -844,9 +849,9 @@ let {{ ubfxCode = ''' Dest = bits(Op1, imm2, imm1); ''' - ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp", - { "code": ubfxCode, - "predicate_test": predicateTest }, []) + ubfxIop = ArmInstObjParams("ubfx", "Ubfx", "RegRegImmImmOp", + { "code": ubfxCode, + "predicate_test": predicateTest }, []) header_output += RegRegImmImmOpDeclare.subst(ubfxIop) decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop) exec_output += PredOpExecute.subst(ubfxIop) @@ -855,9 +860,9 @@ let {{ int32_t resTemp = bits(Op1, imm2, imm1); Dest = resTemp | -(resTemp & (1 << (imm2 - imm1))); ''' - sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp", - { "code": sbfxCode, - "predicate_test": predicateTest }, []) + sbfxIop = ArmInstObjParams("sbfx", "Sbfx", "RegRegImmImmOp", + { "code": sbfxCode, + "predicate_test": predicateTest }, []) header_output += RegRegImmImmOpDeclare.subst(sbfxIop) decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop) exec_output += PredOpExecute.subst(sbfxIop) @@ -865,9 +870,9 @@ let {{ bfcCode = ''' Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1); ''' - bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp", - { "code": bfcCode, - "predicate_test": predicateTest }, []) + bfcIop = ArmInstObjParams("bfc", "Bfc", "RegRegImmImmOp", + { "code": bfcCode, + "predicate_test": predicateTest }, []) header_output += RegRegImmImmOpDeclare.subst(bfcIop) decoder_output += RegRegImmImmOpConstructor.subst(bfcIop) exec_output += PredOpExecute.subst(bfcIop) @@ -876,9 +881,9 @@ let {{ uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1); Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask); ''' - bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp", - { "code": bfiCode, - "predicate_test": predicateTest }, []) + bfiIop = ArmInstObjParams("bfi", "Bfi", "RegRegImmImmOp", + { "code": bfiCode, + "predicate_test": predicateTest }, []) header_output += RegRegImmImmOpDeclare.subst(bfiIop) decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) exec_output += PredOpExecute.subst(bfiIop) @@ -901,9 +906,9 @@ let {{ Dest = MiscOp1; ''' - mrc14Iop = InstObjParams("mrc", "Mrc14", "RegMiscRegImmOp", - { "code": mrc14code, - "predicate_test": predicateTest }, []) + mrc14Iop = ArmInstObjParams("mrc", "Mrc14", "RegMiscRegImmOp", + { "code": mrc14code, + "predicate_test": predicateTest }, []) header_output += RegMiscRegImmOpDeclare.subst(mrc14Iop) decoder_output += RegMiscRegImmOpConstructor.subst(mrc14Iop) exec_output += PredOpExecute.subst(mrc14Iop) @@ -926,10 +931,10 @@ let {{ } MiscDest = Op1; ''' - mcr14Iop = InstObjParams("mcr", "Mcr14", "MiscRegRegImmOp", - { "code": mcr14code, - "predicate_test": predicateTest }, - ["IsSerializeAfter","IsNonSpeculative"]) + mcr14Iop = ArmInstObjParams("mcr", "Mcr14", "MiscRegRegImmOp", + { "code": mcr14code, + "predicate_test": predicateTest }, + ["IsSerializeAfter","IsNonSpeculative"]) header_output += MiscRegRegImmOpDeclare.subst(mcr14Iop) decoder_output += MiscRegRegImmOpConstructor.subst(mcr14Iop) exec_output += PredOpExecute.subst(mcr14Iop) @@ -959,9 +964,9 @@ let {{ Dest = MiscNsBankedOp1; ''' - mrc15Iop = InstObjParams("mrc", "Mrc15", "RegMiscRegImmOp", - { "code": mrc15code, - "predicate_test": predicateTest }, []) + mrc15Iop = ArmInstObjParams("mrc", "Mrc15", "RegMiscRegImmOp", + { "code": mrc15code, + "predicate_test": predicateTest }, []) header_output += RegMiscRegImmOpDeclare.subst(mrc15Iop) decoder_output += RegMiscRegImmOpConstructor.subst(mrc15Iop) exec_output += PredOpExecute.subst(mrc15Iop) @@ -992,10 +997,10 @@ let {{ } MiscNsBankedDest = Op1; ''' - mcr15Iop = InstObjParams("mcr", "Mcr15", "MiscRegRegImmOp", - { "code": mcr15code, - "predicate_test": predicateTest }, - ["IsSerializeAfter","IsNonSpeculative"]) + mcr15Iop = ArmInstObjParams("mcr", "Mcr15", "MiscRegRegImmOp", + { "code": mcr15code, + "predicate_test": predicateTest }, + ["IsSerializeAfter","IsNonSpeculative"]) header_output += MiscRegRegImmOpDeclare.subst(mcr15Iop) decoder_output += MiscRegRegImmOpConstructor.subst(mcr15Iop) exec_output += PredOpExecute.subst(mcr15Iop) @@ -1026,9 +1031,9 @@ let {{ Dest = bits(MiscNsBankedOp164, 63, 32); Dest2 = bits(MiscNsBankedOp164, 31, 0); ''' - mrrc15Iop = InstObjParams("mrrc", "Mrrc15", "MrrcOp", - { "code": mrrc15code, - "predicate_test": predicateTest }, []) + mrrc15Iop = ArmInstObjParams("mrrc", "Mrrc15", "MrrcOp", + { "code": mrrc15code, + "predicate_test": predicateTest }, []) header_output += MrrcOpDeclare.subst(mrrc15Iop) decoder_output += MrrcOpConstructor.subst(mrrc15Iop) exec_output += PredOpExecute.subst(mrrc15Iop) @@ -1059,9 +1064,9 @@ let {{ } MiscNsBankedDest64 = ((uint64_t) Op1 << 32) | Op2; ''' - mcrr15Iop = InstObjParams("mcrr", "Mcrr15", "McrrOp", - { "code": mcrr15code, - "predicate_test": predicateTest }, []) + mcrr15Iop = ArmInstObjParams("mcrr", "Mcrr15", "McrrOp", + { "code": mcrr15code, + "predicate_test": predicateTest }, []) header_output += McrrOpDeclare.subst(mcrr15Iop) decoder_output += McrrOpConstructor.subst(mcrr15Iop) exec_output += PredOpExecute.subst(mcrr15Iop) @@ -1071,9 +1076,9 @@ let {{ NextThumb = true; NextJazelle = true; ''' - enterxIop = InstObjParams("enterx", "Enterx", "PredOp", - { "code": enterxCode, - "predicate_test": predicateTest }, []) + enterxIop = ArmInstObjParams("enterx", "Enterx", "PredOp", + { "code": enterxCode, + "predicate_test": predicateTest }, []) header_output += BasicDeclare.subst(enterxIop) decoder_output += BasicConstructor.subst(enterxIop) exec_output += PredOpExecute.subst(enterxIop) @@ -1082,9 +1087,9 @@ let {{ NextThumb = true; NextJazelle = false; ''' - leavexIop = InstObjParams("leavex", "Leavex", "PredOp", - { "code": leavexCode, - "predicate_test": predicateTest }, []) + leavexIop = ArmInstObjParams("leavex", "Leavex", "PredOp", + { "code": leavexCode, + "predicate_test": predicateTest }, []) header_output += BasicDeclare.subst(leavexIop) decoder_output += BasicConstructor.subst(leavexIop) exec_output += PredOpExecute.subst(leavexIop) @@ -1095,10 +1100,10 @@ let {{ Cpsr = cpsr; fault = checkSETENDEnabled(xc->tcBase(), cpsr); ''' - setendIop = InstObjParams("setend", "Setend", "ImmOp", - { "code": setendCode, - "predicate_test": predicateTest }, - ["IsSerializeAfter","IsNonSpeculative"]) + setendIop = ArmInstObjParams("setend", "Setend", "ImmOp", + { "code": setendCode, + "predicate_test": predicateTest }, + ["IsSerializeAfter","IsNonSpeculative"]) header_output += ImmOpDeclare.subst(setendIop) decoder_output += ImmOpConstructor.subst(setendIop) exec_output += PredOpExecute.subst(setendIop) @@ -1106,9 +1111,9 @@ let {{ clrexCode = ''' LLSCLock = 0; ''' - clrexIop = InstObjParams("clrex", "Clrex","PredOp", - { "code": clrexCode, - "predicate_test": predicateTest },[]) + clrexIop = ArmInstObjParams("clrex", "Clrex","PredOp", + { "code": clrexCode, + "predicate_test": predicateTest },[]) header_output += BasicDeclare.subst(clrexIop) decoder_output += BasicConstructor.subst(clrexIop) exec_output += PredOpExecute.subst(clrexIop) @@ -1143,13 +1148,13 @@ let {{ Request::DST_POC); EA = Op1; ''' - McrDcimvacIop = InstObjParams("mcr", "McrDcimvac", - "MiscRegRegImmOp", - {"memacc_code": McrDcCheckCode, - "postacc_code": "", - "ea_code": McrDcimvacCode, - "predicate_test": predicateTest}, - ['IsStore']) + McrDcimvacIop = ArmInstObjParams("mcr", "McrDcimvac", + "MiscRegRegImmOp", + {"memacc_code": McrDcCheckCode, + "postacc_code": "", + "ea_code": McrDcimvacCode, + "predicate_test": predicateTest}, + ['IsStore']) header_output += MiscRegRegImmMemOpDeclare.subst(McrDcimvacIop) decoder_output += MiscRegRegImmOpConstructor.subst(McrDcimvacIop) exec_output += Mcr15Execute.subst(McrDcimvacIop) + \ @@ -1161,13 +1166,13 @@ let {{ Request::DST_POC); EA = Op1; ''' - McrDccmvacIop = InstObjParams("mcr", "McrDccmvac", - "MiscRegRegImmOp", - {"memacc_code": McrDcCheckCode, - "postacc_code": "", - "ea_code": McrDccmvacCode, - "predicate_test": predicateTest}, - ['IsStore']) + McrDccmvacIop = ArmInstObjParams("mcr", "McrDccmvac", + "MiscRegRegImmOp", + {"memacc_code": McrDcCheckCode, + "postacc_code": "", + "ea_code": McrDccmvacCode, + "predicate_test": predicateTest}, + ['IsStore']) header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvacIop) decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvacIop) exec_output += Mcr15Execute.subst(McrDccmvacIop) + \ @@ -1179,13 +1184,13 @@ let {{ Request::DST_POU); EA = Op1; ''' - McrDccmvauIop = InstObjParams("mcr", "McrDccmvau", - "MiscRegRegImmOp", - {"memacc_code": McrDcCheckCode, - "postacc_code": "", - "ea_code": McrDccmvauCode, - "predicate_test": predicateTest}, - ['IsStore']) + McrDccmvauIop = ArmInstObjParams("mcr", "McrDccmvau", + "MiscRegRegImmOp", + {"memacc_code": McrDcCheckCode, + "postacc_code": "", + "ea_code": McrDccmvauCode, + "predicate_test": predicateTest}, + ['IsStore']) header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvauIop) decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvauIop) exec_output += Mcr15Execute.subst(McrDccmvauIop) + \ @@ -1198,13 +1203,13 @@ let {{ Request::DST_POC); EA = Op1; ''' - McrDccimvacIop = InstObjParams("mcr", "McrDccimvac", - "MiscRegRegImmOp", - {"memacc_code": McrDcCheckCode, - "postacc_code": "", - "ea_code": McrDccimvacCode, - "predicate_test": predicateTest}, - ['IsStore']) + McrDccimvacIop = ArmInstObjParams("mcr", "McrDccimvac", + "MiscRegRegImmOp", + {"memacc_code": McrDcCheckCode, + "postacc_code": "", + "ea_code": McrDccimvacCode, + "predicate_test": predicateTest}, + ['IsStore']) header_output += MiscRegRegImmMemOpDeclare.subst(McrDccimvacIop) decoder_output += MiscRegRegImmOpConstructor.subst(McrDccimvacIop) exec_output += Mcr15Execute.subst(McrDccimvacIop) + \ @@ -1219,10 +1224,10 @@ let {{ EC_TRAPPED_CP15_MCR_MRC); } ''' - isbIop = InstObjParams("isb", "Isb", "ImmOp", - {"code": isbCode, - "predicate_test": predicateTest}, - ['IsSquashAfter']) + isbIop = ArmInstObjParams("isb", "Isb", "ImmOp", + { "code": isbCode, + "predicate_test": predicateTest}, + ['IsSquashAfter']) header_output += ImmOpDeclare.subst(isbIop) decoder_output += ImmOpConstructor.subst(isbIop) exec_output += PredOpExecute.subst(isbIop) @@ -1235,8 +1240,8 @@ let {{ EC_TRAPPED_CP15_MCR_MRC); } ''' - dsbIop = InstObjParams("dsb", "Dsb", "ImmOp", - {"code": dsbCode, + dsbIop = ArmInstObjParams("dsb", "Dsb", "ImmOp", + {"code": dsbCode, "predicate_test": predicateTest}, ['IsReadBarrier', 'IsWriteBarrier', 'IsSerializeAfter']) @@ -1252,18 +1257,18 @@ let {{ EC_TRAPPED_CP15_MCR_MRC); } ''' - dmbIop = InstObjParams("dmb", "Dmb", "ImmOp", - {"code": dmbCode, + dmbIop = ArmInstObjParams("dmb", "Dmb", "ImmOp", + {"code": dmbCode, "predicate_test": predicateTest}, - ['IsReadBarrier', 'IsWriteBarrier']) + ['IsReadBarrier', 'IsWriteBarrier']) header_output += ImmOpDeclare.subst(dmbIop) decoder_output += ImmOpConstructor.subst(dmbIop) exec_output += PredOpExecute.subst(dmbIop) dbgCode = ''' ''' - dbgIop = InstObjParams("dbg", "Dbg", "PredOp", - {"code": dbgCode, + dbgIop = ArmInstObjParams("dbg", "Dbg", "PredOp", + {"code": dbgCode, "predicate_test": predicateTest}) header_output += BasicDeclare.subst(dbgIop) decoder_output += BasicConstructor.subst(dbgIop) @@ -1294,10 +1299,10 @@ let {{ } Cpsr = cpsr; ''' - cpsIop = InstObjParams("cps", "Cps", "ImmOp", - { "code": cpsCode, - "predicate_test": predicateTest }, - ["IsSerializeAfter","IsNonSpeculative"]) + cpsIop = ArmInstObjParams("cps", "Cps", "ImmOp", + { "code": cpsCode, + "predicate_test": predicateTest }, + ["IsSerializeAfter","IsNonSpeculative"]) header_output += ImmOpDeclare.subst(cpsIop) decoder_output += ImmOpConstructor.subst(cpsIop) exec_output += PredOpExecute.subst(cpsIop) diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa index 5cc516703..64dcedda1 100644 --- a/src/arch/arm/isa/insts/misc64.isa +++ b/src/arch/arm/isa/insts/misc64.isa @@ -46,9 +46,9 @@ let {{ fault = std::make_shared(machInst, bits(machInst, 20, 5)); ''' - svcIop = InstObjParams("svc", "Svc64", "ImmOp64", - svcCode, ["IsSyscall", "IsNonSpeculative", - "IsSerializeAfter"]) + svcIop = ArmInstObjParams("svc", "Svc64", "ImmOp64", + svcCode, ["IsSyscall", "IsNonSpeculative", + "IsSerializeAfter"]) header_output = ImmOp64Declare.subst(svcIop) decoder_output = ImmOp64Constructor.subst(svcIop) exec_output = BasicExecute.subst(svcIop) @@ -81,9 +81,9 @@ let {{ } ''' - hvcIop = InstObjParams("hvc", "Hvc64", "ImmOp64", - hvcCode, ["IsSyscall", "IsNonSpeculative", - "IsSerializeAfter"]) + hvcIop = ArmInstObjParams("hvc", "Hvc64", "ImmOp64", + hvcCode, ["IsSyscall", "IsNonSpeculative", + "IsSerializeAfter"]) header_output += ImmOp64Declare.subst(hvcIop) decoder_output += ImmOp64Constructor.subst(hvcIop) exec_output += BasicExecute.subst(hvcIop) @@ -106,8 +106,8 @@ let {{ } ''' - smcIop = InstObjParams("smc", "Smc64", "ImmOp64", - smcCode, ["IsNonSpeculative", "IsSerializeAfter"]) + smcIop = ArmInstObjParams("smc", "Smc64", "ImmOp64", + smcCode, ["IsNonSpeculative", "IsSerializeAfter"]) header_output += ImmOp64Declare.subst(smcIop) decoder_output += ImmOp64Constructor.subst(smcIop) exec_output += BasicExecute.subst(smcIop) @@ -135,16 +135,16 @@ let {{ ''' bfmCode = bfmMaskCode + 'Dest64 = result | (Dest64 & ~bitMask);' - bfmIop = InstObjParams("bfm", "Bfm64", "RegRegImmImmOp64", bfmCode); + bfmIop = ArmInstObjParams("bfm", "Bfm64", "RegRegImmImmOp64", bfmCode); subst("RegRegImmImmOp64", bfmIop) ubfmCode = bfmMaskCode + 'Dest64 = result;' - ubfmIop = InstObjParams("ubfm", "Ubfm64", "RegRegImmImmOp64", ubfmCode); + ubfmIop = ArmInstObjParams("ubfm", "Ubfm64", "RegRegImmImmOp64", ubfmCode); subst("RegRegImmImmOp64", ubfmIop) sbfmCode = bfmMaskCode + \ 'Dest64 = result | (bits(Op164, imm2) ? topBits : 0);' - sbfmIop = InstObjParams("sbfm", "Sbfm64", "RegRegImmImmOp64", sbfmCode); + sbfmIop = ArmInstObjParams("sbfm", "Sbfm64", "RegRegImmImmOp64", sbfmCode); subst("RegRegImmImmOp64", sbfmIop) extrCode = ''' @@ -154,39 +154,39 @@ let {{ Dest64 = (Op164 << (intWidth - imm)) | (Op264 >> imm); } ''' - extrIop = InstObjParams("extr", "Extr64", "RegRegRegImmOp64", extrCode); + extrIop = ArmInstObjParams("extr", "Extr64", "RegRegRegImmOp64", extrCode); subst("RegRegRegImmOp64", extrIop); unknownCode = ''' return std::make_shared(machInst, true); ''' - unknown64Iop = InstObjParams("unknown", "Unknown64", "UnknownOp64", - unknownCode) + unknown64Iop = ArmInstObjParams("unknown", "Unknown64", "UnknownOp64", + unknownCode) header_output += BasicDeclare.subst(unknown64Iop) decoder_output += BasicConstructor64.subst(unknown64Iop) exec_output += BasicExecute.subst(unknown64Iop) - isbIop = InstObjParams("isb", "Isb64", "ArmStaticInst", "", - ['IsSquashAfter']) + isbIop = ArmInstObjParams("isb", "Isb64", "ArmStaticInst", "", + ['IsSquashAfter']) header_output += BasicDeclare.subst(isbIop) decoder_output += BasicConstructor64.subst(isbIop) exec_output += BasicExecute.subst(isbIop) - dsbIop = InstObjParams("dsb", "Dsb64", "ArmStaticInst", "", - ['IsReadBarrier', 'IsWriteBarrier', - 'IsSerializeAfter']) + dsbIop = ArmInstObjParams("dsb", "Dsb64", "ArmStaticInst", "", + ['IsReadBarrier', 'IsWriteBarrier', + 'IsSerializeAfter']) header_output += BasicDeclare.subst(dsbIop) decoder_output += BasicConstructor64.subst(dsbIop) exec_output += BasicExecute.subst(dsbIop) - dmbIop = InstObjParams("dmb", "Dmb64", "ArmStaticInst", "", - ['IsReadBarrier', 'IsWriteBarrier']) + dmbIop = ArmInstObjParams("dmb", "Dmb64", "ArmStaticInst", "", + ['IsReadBarrier', 'IsWriteBarrier']) header_output += BasicDeclare.subst(dmbIop) decoder_output += BasicConstructor64.subst(dmbIop) exec_output += BasicExecute.subst(dmbIop) - clrexIop = InstObjParams("clrex", "Clrex64", "ArmStaticInst", - "LLSCLock = 0;") + clrexIop = ArmInstObjParams("clrex", "Clrex64", "ArmStaticInst", + "LLSCLock = 0;") header_output += BasicDeclare.subst(clrexIop) decoder_output += BasicConstructor64.subst(clrexIop) exec_output += BasicExecute.subst(clrexIop) @@ -197,8 +197,8 @@ let {{ bits(machInst, 20, 5)); ''' - brkIop = InstObjParams("brk", "Brk64", "ImmOp64", - brkCode, ["IsSerializeAfter"]) + brkIop = ArmInstObjParams("brk", "Brk64", "ImmOp64", + brkCode, ["IsSerializeAfter"]) header_output += ImmOp64Declare.subst(brkIop) decoder_output += ImmOp64Constructor.subst(brkIop) exec_output += BasicExecute.subst(brkIop) @@ -219,8 +219,8 @@ let {{ ''' - hltIop = InstObjParams("hlt", "Hlt64", "ImmOp64", - hltCode, ["IsNonSpeculative", "IsSerializeAfter"]) + hltIop = ArmInstObjParams("hlt", "Hlt64", "ImmOp64", hltCode, + ["IsNonSpeculative", "IsSerializeAfter"]) header_output += ImmOp64Declare.subst(hltIop) decoder_output += SemihostConstructor64.subst(hltIop) exec_output += BasicExecute.subst(hltIop) diff --git a/src/arch/arm/isa/insts/mult.isa b/src/arch/arm/isa/insts/mult.isa index 6885be150..77a2f709b 100644 --- a/src/arch/arm/isa/insts/mult.isa +++ b/src/arch/arm/isa/insts/mult.isa @@ -84,15 +84,14 @@ let {{ Name = mnem.capitalize() if unCc: - iop = InstObjParams(mnem, Name, base, - {"code" : code, - "predicate_test": pickPredicate(code), - "op_class": "IntMultOp" }) + iop = ArmInstObjParams(mnem, Name, base, + { "code" : code, "predicate_test": pickPredicate(code), + "op_class": "IntMultOp" }) if doCc: - iopCc = InstObjParams(mnem + "s", Name + "Cc", base, - {"code" : code + ccCode, - "predicate_test": pickPredicate(code + ccCode), - "op_class": "IntMultOp" }) + iopCc = ArmInstObjParams(mnem + "s", Name + "Cc", base, + { "code" : code + ccCode, + "predicate_test": pickPredicate(code + ccCode), + "op_class": "IntMultOp" }) if regs == 3: declare = Mult3Declare diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa index 2d25f3611..756abdc90 100644 --- a/src/arch/arm/isa/insts/neon.isa +++ b/src/arch/arm/isa/insts/neon.isa @@ -1222,12 +1222,12 @@ let {{ eWalkCode += ''' FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "RegRegRegImmOp" if byElem else "RegRegRegOp", - { "code": eWalkCode, - "r_count": rCount, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "RegRegRegImmOp" if byElem else "RegRegRegOp", + { "code": eWalkCode, + "r_count": rCount, + "predicate_test": predicateTest, + "op_class": opClass }, []) if byElem: header_output += NeonRegRegRegImmOpDeclare.subst(iop) else: @@ -1310,12 +1310,12 @@ let {{ eWalkCode += ''' FpDestP%(reg)d = destRegs[%(reg)d]; ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "FpRegRegRegOp", - { "code": eWalkCode, - "r_count": rCount, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "FpRegRegRegOp", + { "code": eWalkCode, + "r_count": rCount, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += NeonRegRegRegOpDeclare.subst(iop) exec_output += NeonEqualRegExecute.subst(iop) for type in types: @@ -1374,12 +1374,12 @@ let {{ eWalkCode += ''' FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "RegRegRegOp", - { "code": eWalkCode, - "r_count": 2, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "RegRegRegOp", + { "code": eWalkCode, + "r_count": 2, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += NeonRegRegRegOpDeclare.subst(iop) exec_output += NeonUnequalRegExecute.subst(iop) for type in types: @@ -1437,12 +1437,12 @@ let {{ eWalkCode += ''' FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "RegRegRegImmOp", - { "code": eWalkCode, - "r_count": rCount, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "RegRegRegImmOp", + { "code": eWalkCode, + "r_count": rCount, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += NeonRegRegRegImmOpDeclare.subst(iop) exec_output += NeonEqualRegExecute.subst(iop) for type in types: @@ -1489,12 +1489,12 @@ let {{ eWalkCode += ''' FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "RegRegRegImmOp", - { "code": eWalkCode, - "r_count": rCount, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "RegRegRegImmOp", + { "code": eWalkCode, + "r_count": rCount, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += NeonRegRegRegImmOpDeclare.subst(iop) exec_output += NeonUnequalRegExecute.subst(iop) for type in types: @@ -1539,12 +1539,12 @@ let {{ eWalkCode += ''' FpDestP%(reg)d = destRegs[%(reg)d]; ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "FpRegRegRegImmOp", - { "code": eWalkCode, - "r_count": rCount, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "FpRegRegRegImmOp", + { "code": eWalkCode, + "r_count": rCount, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += NeonRegRegRegImmOpDeclare.subst(iop) exec_output += NeonEqualRegExecute.subst(iop) for type in types: @@ -1596,12 +1596,12 @@ let {{ eWalkCode += ''' FpDestP%(reg)d_uw = letoh(destRegs.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "RegRegImmOp", - { "code": eWalkCode, - "r_count": rCount, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "RegRegImmOp", + { "code": eWalkCode, + "r_count": rCount, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += NeonRegRegImmOpDeclare.subst(iop) exec_output += NeonEqualRegExecute.subst(iop) for type in types: @@ -1640,12 +1640,12 @@ let {{ eWalkCode += ''' FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "RegRegImmOp", - { "code": eWalkCode, - "r_count": 2, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "RegRegImmOp", + { "code": eWalkCode, + "r_count": 2, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += NeonRegRegImmOpDeclare.subst(iop) exec_output += NeonUnequalRegExecute.subst(iop) for type in types: @@ -1684,12 +1684,12 @@ let {{ eWalkCode += ''' FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "RegRegImmOp", - { "code": eWalkCode, - "r_count": 2, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "RegRegImmOp", + { "code": eWalkCode, + "r_count": 2, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += NeonRegRegImmOpDeclare.subst(iop) exec_output += NeonUnequalRegExecute.subst(iop) for type in types: @@ -1727,12 +1727,12 @@ let {{ eWalkCode += ''' FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "RegRegOp", - { "code": eWalkCode, - "r_count": rCount, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "RegRegOp", + { "code": eWalkCode, + "r_count": rCount, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += NeonRegRegOpDeclare.subst(iop) exec_output += NeonEqualRegExecute.subst(iop) for type in types: @@ -1769,12 +1769,12 @@ let {{ eWalkCode += ''' FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "RegRegImmOp", - { "code": eWalkCode, - "r_count": rCount, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "RegRegImmOp", + { "code": eWalkCode, + "r_count": rCount, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += NeonRegRegImmOpDeclare.subst(iop) exec_output += NeonEqualRegExecute.subst(iop) for type in types: @@ -1804,12 +1804,12 @@ let {{ FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]); FpOp1P%(reg)d_uw = letoh(srcReg1.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "RegRegOp", - { "code": eWalkCode, - "r_count": rCount, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "RegRegOp", + { "code": eWalkCode, + "r_count": rCount, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += NeonRegRegOpDeclare.subst(iop) exec_output += NeonEqualRegExecute.subst(iop) for type in types: @@ -1870,12 +1870,12 @@ let {{ eWalkCode += ''' FpDestP%(reg)d = destRegs[%(reg)d]; ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "FpRegRegOp", - { "code": eWalkCode, - "r_count": rCount, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "FpRegRegOp", + { "code": eWalkCode, + "r_count": rCount, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += NeonRegRegOpDeclare.subst(iop) exec_output += NeonEqualRegExecute.subst(iop) for type in types: @@ -1914,12 +1914,12 @@ let {{ eWalkCode += ''' FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "RegRegOp", - { "code": eWalkCode, - "r_count": rCount, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "RegRegOp", + { "code": eWalkCode, + "r_count": rCount, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += NeonRegRegOpDeclare.subst(iop) exec_output += NeonUnequalRegExecute.subst(iop) for type in types: @@ -1958,12 +1958,12 @@ let {{ eWalkCode += ''' FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "RegRegOp", - { "code": eWalkCode, - "r_count": 2, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "RegRegOp", + { "code": eWalkCode, + "r_count": 2, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += NeonRegRegOpDeclare.subst(iop) exec_output += NeonUnequalRegExecute.subst(iop) for type in types: @@ -1996,12 +1996,12 @@ let {{ eWalkCode += ''' FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "RegImmOp", - { "code": eWalkCode, - "r_count": rCount, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "RegImmOp", + { "code": eWalkCode, + "r_count": rCount, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += NeonRegImmOpDeclare.subst(iop) exec_output += NeonEqualRegExecute.subst(iop) for type in types: @@ -2040,12 +2040,12 @@ let {{ eWalkCode += ''' FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "RegRegOp", - { "code": eWalkCode, - "r_count": 2, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "RegRegOp", + { "code": eWalkCode, + "r_count": 2, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += NeonRegRegOpDeclare.subst(iop) exec_output += NeonUnequalRegExecute.subst(iop) for type in types: @@ -3922,12 +3922,12 @@ let {{ eWalkCode += ''' FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "RegRegOp", - { "code": eWalkCode, - "r_count": rCount, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "RegRegOp", + { "code": eWalkCode, + "r_count": rCount, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += NeonRegRegOpDeclare.subst(iop) exec_output += NeonEqualRegExecute.subst(iop) for type in types: @@ -4008,12 +4008,12 @@ let {{ eWalkCode += ''' FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "RegRegRegImmOp", - { "code": eWalkCode, - "r_count": rCount, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "RegRegRegImmOp", + { "code": eWalkCode, + "r_count": rCount, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += NeonRegRegRegImmOpDeclare.subst(iop) exec_output += NeonEqualRegExecute.subst(iop) for type in types: @@ -4086,11 +4086,11 @@ let {{ FpDestP0_uw = letoh(destReg.regs[0]); FpDestP1_uw = letoh(destReg.regs[1]); ''' - iop = InstObjParams(name, Name, - "RegRegRegOp", - { "code": code, - "predicate_test": predicateTest, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "RegRegRegOp", + { "code": code, + "predicate_test": predicateTest, + "op_class": opClass }, []) header_output += RegRegRegOpDeclare.subst(iop) decoder_output += RegRegRegOpConstructor.subst(iop) exec_output += PredOpExecute.subst(iop) diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa index 36db47451..6b8edddbf 100644 --- a/src/arch/arm/isa/insts/neon64.isa +++ b/src/arch/arm/isa/insts/neon64.isa @@ -134,11 +134,11 @@ let {{ eWalkCode += ''' AA64FpDestP%(reg)d_uw = 0; ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "DataX2RegImmOp" if byElem else "DataX2RegOp", - { "code": eWalkCode, - "r_count": rCount, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "DataX2RegImmOp" if byElem else "DataX2RegOp", + { "code": eWalkCode, + "r_count": rCount, + "op_class": opClass }, []) iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" if byElem: header_output += NeonX2RegImmOpDeclare.subst(iop) @@ -244,11 +244,11 @@ let {{ eWalkCode += ''' AA64FpDestP%(reg)d_uw = 0;''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "DataX2RegImmOp" if byElem else "DataX2RegOp", - { "code": eWalkCode, - "r_count": 2, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "DataX2RegImmOp" if byElem else "DataX2RegOp", + { "code": eWalkCode, + "r_count": 2, + "op_class": opClass }, []) iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" if byElem: header_output += NeonX2RegImmOpDeclare.subst(iop) @@ -332,11 +332,11 @@ let {{ eWalkCode += ''' AA64FpDestP%(reg)d_uw = 0; ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "DataX1RegImmOp" if hasImm else "DataX1RegOp", - { "code": eWalkCode, - "r_count": rCount, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "DataX1RegImmOp" if hasImm else "DataX1RegOp", + { "code": eWalkCode, + "r_count": rCount, + "op_class": opClass }, []) iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" if hasImm: header_output += NeonX1RegImmOpDeclare.subst(iop) @@ -384,11 +384,11 @@ let {{ eWalkCode += ''' AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "DataX1RegImmOp" if hasImm else "DataX1RegOp", - { "code": eWalkCode, - "r_count": 2, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "DataX1RegImmOp" if hasImm else "DataX1RegOp", + { "code": eWalkCode, + "r_count": 2, + "op_class": opClass }, []) iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" if hasImm: header_output += NeonX1RegImmOpDeclare.subst(iop) @@ -456,11 +456,11 @@ let {{ AA64FpDestP%(reg)d_uw = 0; ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "DataX1RegImmOp" if hasImm else "DataX1RegOp", - { "code": eWalkCode, - "r_count": 2, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, + "DataX1RegImmOp" if hasImm else "DataX1RegOp", + { "code": eWalkCode, + "r_count": 2, + "op_class": opClass }, []) iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" if hasImm: header_output += NeonX1RegImmOpDeclare.subst(iop) @@ -492,11 +492,10 @@ let {{ eWalkCode += ''' AA64FpDestP%(reg)d_uw = 0; ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "DataX2RegOp", - { "code": eWalkCode, - "r_count": rCount, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, "DataX2RegOp", + { "code": eWalkCode, + "r_count": rCount, + "op_class": opClass }, []) iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" header_output += NeonX2RegOpDeclare.subst(iop) exec_output += NeonXEqualRegOpExecute.subst(iop) @@ -528,11 +527,10 @@ let {{ eWalkCode += ''' AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "DataX1Reg2ImmOp", - { "code": eWalkCode, - "r_count": rCount, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, "DataX1Reg2ImmOp", + { "code": eWalkCode, + "r_count": rCount, + "op_class": opClass }, []) iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" header_output += NeonX1Reg2ImmOpDeclare.subst(iop) exec_output += NeonXEqualRegOpExecute.subst(iop) @@ -566,11 +564,10 @@ let {{ eWalkCode += ''' AA64FpDestP%(reg)d_uw = 0; ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "DataX1RegOp", - { "code": eWalkCode, - "r_count": rCount, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, "DataX1RegOp", + { "code": eWalkCode, + "r_count": rCount, + "op_class": opClass }, []) iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" header_output += NeonX1RegOpDeclare.subst(iop) exec_output += NeonXEqualRegOpExecute.subst(iop) @@ -613,11 +610,10 @@ let {{ eWalkCode += ''' AA64FpDestP%(reg)d_uw = 0; ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "DataX1RegOp", - { "code": eWalkCode, - "r_count": rCount, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, "DataX1RegOp", + { "code": eWalkCode, + "r_count": rCount, + "op_class": opClass }, []) iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" header_output += NeonX1RegOpDeclare.subst(iop) if long: @@ -666,11 +662,10 @@ let {{ eWalkCode += ''' AA64FpDestP%(reg)d_uw = 0; ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "DataX1RegOp", - { "code": eWalkCode, - "r_count": rCount, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, "DataX1RegOp", + { "code": eWalkCode, + "r_count": rCount, + "op_class": opClass }, []) iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" header_output += NeonX1RegOpDeclare.subst(iop) exec_output += NeonXUnequalRegOpExecute.subst(iop) @@ -709,11 +704,10 @@ let {{ eWalkCode += ''' AA64FpDestP%(reg)d_uw = 0; ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "DataXImmOnlyOp", - { "code": eWalkCode, - "r_count": rCount, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, "DataXImmOnlyOp", + { "code": eWalkCode, + "r_count": rCount, + "op_class": opClass }, []) iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" header_output += NeonX1RegImmOnlyOpDeclare.subst(iop) exec_output += NeonXEqualRegOpExecute.subst(iop) @@ -739,11 +733,10 @@ let {{ eWalkCode += ''' AA64FpDestP%(reg)d_uw = 0; ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "DataX1RegOp", - { "code": eWalkCode, - "r_count": rCount, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, "DataX1RegOp", + { "code": eWalkCode, + "r_count": rCount, + "op_class": opClass }, []) iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" header_output += NeonX1RegOpDeclare.subst(iop) exec_output += NeonXEqualRegOpExecute.subst(iop) @@ -772,11 +765,10 @@ let {{ eWalkCode += ''' AA64FpDestP%(reg)d_uw = 0; ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "DataX2RegImmOp", - { "code": eWalkCode, - "r_count": rCount, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, "DataX2RegImmOp", + { "code": eWalkCode, + "r_count": rCount, + "op_class": opClass }, []) iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" header_output += NeonX2RegImmOpDeclare.subst(iop) exec_output += NeonXEqualRegOpExecute.subst(iop) @@ -801,11 +793,10 @@ let {{ eWalkCode += ''' AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "DataX1RegImmOp", - { "code": eWalkCode, - "r_count": rCount, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, "DataX1RegImmOp", + { "code": eWalkCode, + "r_count": rCount, + "op_class": opClass }, []) iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" header_output += NeonX1RegImmOpDeclare.subst(iop) exec_output += NeonXEqualRegOpExecute.subst(iop) @@ -832,11 +823,10 @@ let {{ eWalkCode += ''' %sDest = srcReg.elements[imm]; ''' % gprSpec - iop = InstObjParams(name, Name, - "DataX1RegImmOp", - { "code": eWalkCode, - "r_count": rCount, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, "DataX1RegImmOp", + { "code": eWalkCode, + "r_count": rCount, + "op_class": opClass }, []) header_output += NeonX1RegImmOpDeclare.subst(iop) exec_output += NeonXEqualRegOpExecute.subst(iop) for type in types: @@ -897,11 +887,10 @@ let {{ code += ''' AA64FpDestP%(reg)d_uw = 0; ''' % { "reg" : reg } - iop = InstObjParams(name, Name, - "DataX2RegOp", - { "code": code, - "r_count": rCount, - "op_class": opClass }, []) + iop = ArmInstObjParams(name, Name, "DataX2RegOp", + { "code": code, + "r_count": rCount, + "op_class": opClass }, []) iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest" header_output += NeonX2RegOpDeclare.subst(iop) exec_output += NeonXEqualRegOpExecute.subst(iop) diff --git a/src/arch/arm/isa/insts/neon64_mem.isa b/src/arch/arm/isa/insts/neon64_mem.isa index 80741fb94..4977c4192 100644 --- a/src/arch/arm/isa/insts/neon64_mem.isa +++ b/src/arch/arm/isa/insts/neon64_mem.isa @@ -139,7 +139,7 @@ let {{ loadMemAccCode = convCode + regSetCode storeMemAccCode = regGetCode + convCode - loadIop = InstObjParams(name + 'ld', + loadIop = ArmInstObjParams(name + 'ld', 'MicroNeonLoad64', 'MicroNeonMemOp', { 'mem_decl' : memDecl, @@ -149,7 +149,7 @@ let {{ [ 'IsMicroop', 'IsLoad' ]) loadIop.snippets["memacc_code"] += zeroSveVecRegUpperPartCode % \ "AA64FpDest" - storeIop = InstObjParams(name + 'st', + storeIop = ArmInstObjParams(name + 'st', 'MicroNeonStore64', 'MicroNeonMemOp', { 'mem_decl' : memDecl, @@ -266,9 +266,9 @@ let {{ } ''' - iop = InstObjParams(name, Name, 'MicroNeonMixOp64', - { 'code' : eCode, 'op_class' : 'No_OpClass' }, - ['IsMicroop']) + iop = ArmInstObjParams(name, Name, 'MicroNeonMixOp64', + { 'code' : eCode, 'op_class' : 'No_OpClass' }, + ['IsMicroop']) header_output += MicroNeonMixDeclare64.subst(iop) exec_output += MicroNeonMixExecute64.subst(iop) @@ -329,9 +329,9 @@ let {{ output[%(v)d], %(p)d, 0x2); ''' % { 'v': v, 'p': p} - iop = InstObjParams(name, Name, 'MicroNeonMixOp64', - { 'code' : eCode, 'op_class' : 'No_OpClass' }, - ['IsMicroop']) + iop = ArmInstObjParams(name, Name, 'MicroNeonMixOp64', + { 'code' : eCode, 'op_class' : 'No_OpClass' }, + ['IsMicroop']) header_output += MicroNeonMixDeclare64.subst(iop) exec_output += MicroNeonMixExecute64.subst(iop) @@ -398,8 +398,8 @@ let {{ output[%(v)d], %(p)d, 0x2); ''' % { 'v' : v, 'p' : p } - iop = InstObjParams(name, Name, 'MicroNeonMixLaneOp64', - { 'code' : eCode }, ['IsMicroop']) + iop = ArmInstObjParams(name, Name, 'MicroNeonMixLaneOp64', + { 'code' : eCode }, ['IsMicroop']) header_output += MicroNeonMixLaneDeclare64.subst(iop) exec_output += MicroNeonMixExecute64.subst(iop) @@ -447,8 +447,8 @@ let {{ output[%(v)d], %(p)d, 0x2); ''' % { 'v' : v, 'p' : p } - iop = InstObjParams(name, Name, 'MicroNeonMixLaneOp64', - { 'code' : eCode }, ['IsMicroop']) + iop = ArmInstObjParams(name, Name, 'MicroNeonMixLaneOp64', + { 'code' : eCode }, ['IsMicroop']) header_output += MicroNeonMixLaneDeclare64.subst(iop) exec_output += MicroNeonMixExecute64.subst(iop) @@ -469,19 +469,21 @@ let {{ let {{ - iop = InstObjParams('vldmult64', 'VldMult64', 'VldMultOp64', '', []) + iop = ArmInstObjParams('vldmult64', 'VldMult64', 'VldMultOp64', '', []) header_output += VMemMultDeclare64.subst(iop) decoder_output += VMemMultConstructor64.subst(iop) - iop = InstObjParams('vstmult64', 'VstMult64', 'VstMultOp64', '', []) + iop = ArmInstObjParams('vstmult64', 'VstMult64', 'VstMultOp64', '', []) header_output += VMemMultDeclare64.subst(iop) decoder_output += VMemMultConstructor64.subst(iop) - iop = InstObjParams('vldsingle64', 'VldSingle64', 'VldSingleOp64', '', []) + iop = ArmInstObjParams( + 'vldsingle64', 'VldSingle64', 'VldSingleOp64', '', []) header_output += VMemSingleDeclare64.subst(iop) decoder_output += VMemSingleConstructor64.subst(iop) - iop = InstObjParams('vstsingle64', 'VstSingle64', 'VstSingleOp64', '', []) + iop = ArmInstObjParams( + 'vstsingle64', 'VstSingle64', 'VstSingleOp64', '', []) header_output += VMemSingleDeclare64.subst(iop) decoder_output += VMemSingleConstructor64.subst(iop) diff --git a/src/arch/arm/isa/insts/pauth.isa b/src/arch/arm/isa/insts/pauth.isa index 4806e6a98..ee3f2d31f 100644 --- a/src/arch/arm/isa/insts/pauth.isa +++ b/src/arch/arm/isa/insts/pauth.isa @@ -78,7 +78,7 @@ let {{ "op2": 'Op164', "op": opcode } - iop = InstObjParams(mnem, mnem, templateBase+"Op", code, optArgs) + iop = ArmInstObjParams(mnem, mnem, templateBase+"Op", code, optArgs) header_output += eval(templateBase + "Declare").subst(iop) decoder_output += eval(templateBase + "Constructor").subst(iop) exec_output += BasicExecute.subst(iop) @@ -94,7 +94,7 @@ let {{ """ regoptype = 'RegOp' - iop = InstObjParams(mnem, mnem, regoptype, code, optArgs) + iop = ArmInstObjParams(mnem, mnem, regoptype, code, optArgs) header_output += eval(templateBase + "Declare").subst(iop) decoder_output += eval(templateBase + "Constructor").subst(iop) exec_output += BasicExecute.subst(iop) diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa index 0b0adf445..03775ca9b 100644 --- a/src/arch/arm/isa/insts/sve.isa +++ b/src/arch/arm/isa/insts/sve.isa @@ -1263,8 +1263,8 @@ let {{ %(op)s AA64FpDest_x[i] = destElem; }''' % {'op': op} - iop = InstObjParams(name, 'Sve' + Name, 'SveAdrOp', - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveAdrOp', + {'code': code, 'op_class': opClass}, []) header_output += SveAdrOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) for type in types: @@ -1301,7 +1301,7 @@ let {{ CondCodesC = !last; CondCodesV = false; '''%{'op': op, 'stype': srcType} - iop = InstObjParams(name, 'Sve' + Name, 'SveWhileOp', + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveWhileOp', {'code': code, 'op_class': opClass, 'srcIs32b': srcSize}, []) iop.snippets['code'] = extraPrologCode + iop.snippets['code'] header_output += SveWhileOpDeclare.subst(iop) @@ -1326,7 +1326,7 @@ let {{ CondCodesV = !CondCodesC; } ''' % {'op': op} - iop = InstObjParams(name, 'Sve' + Name, 'SveCompTermOp', + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveCompTermOp', {'code': code, 'op_class': opClass}, []) header_output += SveCompTermOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) @@ -1361,7 +1361,7 @@ let {{ else: code += ''' %(op)s''' % {'op': op} - iop = InstObjParams(name, 'Sve' + Name, 'SvePredCountOp', + iop = ArmInstObjParams(name, 'Sve' + Name, 'SvePredCountOp', {'code': code, 'op_class': opClass, 'srcIs32b': srcSize, 'destIsVec': destType}, []) header_output += SvePredCountOpDeclare.subst(iop) @@ -1384,8 +1384,8 @@ let {{ } XDest = count; ''' - iop = InstObjParams(name, 'Sve' + Name, 'SvePredCountPredOp', - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, 'SvePredCountPredOp', + {'code': code, 'op_class': opClass}, []) header_output += SvePredCountPredOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) for type in types: @@ -1414,7 +1414,7 @@ let {{ for (unsigned i = 0; i < eCount; i++) { AA64FpDest_x[i] = srcElem1 + i * srcElem2; }''' - iop = InstObjParams('index', 'SveIndex'+fmt, 'SveIndex'+fmt+'Op', + iop = ArmInstObjParams('index', 'SveIndex'+fmt, 'SveIndex'+fmt+'Op', {'code': code, 'op_class': 'SimdAluOp'}) if fmt == IndexFormat.ImmImm: header_output += SveIndexIIOpDeclare.subst(iop) @@ -1456,10 +1456,10 @@ let {{ code += ''' AA64FpDest_xd[i] = destElem; }''' - iop = InstObjParams(name, 'Sve' + Name, - 'SveUnaryPredOp' if predType != PredType.NONE - else 'SveUnaryUnpredOp', - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, + 'SveUnaryPredOp' if predType != PredType.NONE + else 'SveUnaryUnpredOp', + {'code': code, 'op_class': opClass}, []) if predType != PredType.NONE: header_output += SveWideningUnaryPredOpDeclare.subst(iop) else: @@ -1499,10 +1499,10 @@ let {{ code += ''' AA64FpDest_x[i] = destElem; }''' - iop = InstObjParams(name, 'Sve' + Name, - 'SveUnaryPredOp' if predType != PredType.NONE - else 'SveUnaryUnpredOp', - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, + 'SveUnaryPredOp' if predType != PredType.NONE + else 'SveUnaryUnpredOp', + {'code': code, 'op_class': opClass}, []) if predType != PredType.NONE: header_output += SveUnaryPredOpDeclare.subst(iop) else: @@ -1559,8 +1559,8 @@ let {{ 'assign': assign_code } - iop = InstObjParams(name, 'Sve' + Name, 'SveUnaryPredOp', - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveUnaryPredOp', + {'code': code, 'op_class': opClass}, []) header_output += SveWideningUnaryPredOpDeclare.subst(iop) exec_output += SveWideningOpExecute.subst(iop) for type in types: @@ -1590,8 +1590,8 @@ let {{ } AA64FpDest_x[0] = destElem; ''' % {'op': op, 'identity': identity} - iop = InstObjParams(name, 'Sve' + Name, 'SveReducOp', - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveReducOp', + {'code': code, 'op_class': opClass}, []) header_output += SveReducOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) for type in types: @@ -1620,8 +1620,8 @@ let {{ AA64FpDest_xd[i] = 0; } ''' % {'op': op, 'identity': identity} - iop = InstObjParams(name, 'Sve' + Name, 'SveReducOp', - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveReducOp', + {'code': code, 'op_class': opClass}, []) header_output += SveWideningReducOpDeclare.subst(iop) exec_output += SveWideningOpExecute.subst(iop) for type in types: @@ -1669,8 +1669,8 @@ let {{ AA64FpDest_x[i] = 0; // zero upper part } ''' % {'op': op, 'identity': identity} - iop = InstObjParams(name, 'Sve' + Name, 'SveReducOp', - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveReducOp', + {'code': code, 'op_class': opClass}, []) header_output += SveReducOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) for type in types: @@ -1711,7 +1711,7 @@ let {{ code += ''' AA64FpDest_x[i] = destElem; }''' - iop = InstObjParams(name, 'Sve' + Name, + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveBinImmPredOp' if predType != PredType.NONE else 'SveBinImmUnpredConstrOp', {'code': code, 'op_class': opClass}, []) @@ -1759,7 +1759,7 @@ let {{ code += ''' AA64FpDest_x[i] = destElem; }''' - iop = InstObjParams(name, 'Sve' + Name, + iop = ArmInstObjParams(name, 'Sve' + Name, 'Sve%sWideImm%sOp' % ( 'Unary' if isUnary else 'Bin', 'Unpred' if predType == PredType.NONE else 'Pred'), @@ -1812,10 +1812,10 @@ let {{ code += ''' AA64FpDest_x[i] = destElem; }''' - iop = InstObjParams(name, 'Sve' + Name, - 'SveBinDestrPredOp' if predType != PredType.NONE - else 'SveBinUnpredOp', - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, + 'SveBinDestrPredOp' if predType != PredType.NONE + else 'SveBinUnpredOp', + {'code': code, 'op_class': opClass}, []) if predType != PredType.NONE: header_output += SveBinDestrPredOpDeclare.subst(iop) else: @@ -1857,8 +1857,8 @@ let {{ baseClass = 'SveBinIdxUnpredOp' - iop = InstObjParams(name, 'Sve' + Name, baseClass, - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, baseClass, + {'code': code, 'op_class': opClass}, []) header_output += SveBinIdxUnpredOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) for type in types: @@ -1913,8 +1913,8 @@ let {{ baseClass = 'SveBinDestrPredOp' else: baseClass = 'SveBinConstrPredOp' - iop = InstObjParams(name, 'Sve' + Name, baseClass, - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, baseClass, + {'code': code, 'op_class': opClass}, []) if predType == PredType.NONE: header_output += SveBinUnpredOpDeclare.subst(iop) elif isDestructive: @@ -1963,8 +1963,8 @@ let {{ CondCodesV = 0;''' extraPrologCode += ''' auto& destPred = PDest;''' - iop = InstObjParams(name, 'Sve' + Name, 'SvePredLogicalOp', - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, 'SvePredLogicalOp', + {'code': code, 'op_class': opClass}, []) iop.snippets['code'] = extraPrologCode + iop.snippets['code'] header_output += SvePredLogicalOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) @@ -1981,8 +1981,8 @@ let {{ unsigned eCount = ArmStaticInst::getCurSveVecLen( xc->tcBase());''' code += iterCode - iop = InstObjParams(name, 'Sve' + Name, 'SvePredBinPermOp', - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, 'SvePredBinPermOp', + {'code': code, 'op_class': opClass}, []) header_output += SveBinUnpredOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) for type in types: @@ -2018,9 +2018,9 @@ let {{ }''' % {'op': op, 'src_elem_2_ty': 'Element' if isImm else 'const Element&', 'src_elem_2': 'imm' if isImm else 'AA64FpOp2_x[i]'} - iop = InstObjParams(name, 'Sve' + Name, - 'SveCmpImmOp' if isImm else 'SveCmpOp', - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, + 'SveCmpImmOp' if isImm else 'SveCmpOp', + {'code': code, 'op_class': opClass}, []) iop.snippets['code'] = extraPrologCode + iop.snippets['code'] if isImm: header_output += SveCmpImmOpDeclare.subst(iop) @@ -2048,8 +2048,8 @@ let {{ } AA64FpDest_x[i] = destElem; }''' % {'op': op} - iop = InstObjParams(name, 'Sve' + Name, 'SveTerPredOp', - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveTerPredOp', + {'code': code, 'op_class': opClass}, []) header_output += SveTerPredOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) for type in types: @@ -2086,8 +2086,8 @@ let {{ AA64FpDest_x[i] = auxDest[i]; }''' % {'op': op} - iop = InstObjParams(name, 'Sve' + Name, 'SveBinIdxUnpredOp', - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveBinIdxUnpredOp', + {'code': code, 'op_class': opClass}, []) header_output += SveBinIdxUnpredOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) for type in types: @@ -2109,8 +2109,8 @@ let {{ %(op)s AA64FpDest_x[i] = destElem; }''' % {'op': op} - iop = InstObjParams(name, 'Sve' + Name, 'SveTerImmUnpredOp', - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveTerImmUnpredOp', + {'code': code, 'op_class': opClass}, []) header_output += SveTerImmUnpredOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) for type in types: @@ -2138,8 +2138,8 @@ let {{ destPred.noneActive(destPred, eCount); CondCodesC = !destPred.lastActive(destPred, eCount); CondCodesV = 0;''' - iop = InstObjParams(name, 'Sve' + Name, 'SvePtrueOp', - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, 'SvePtrueOp', + {'code': code, 'op_class': opClass}, []) iop.snippets['code'] = extraPrologCode + iop.snippets['code'] header_output += SvePtrueOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) @@ -2186,8 +2186,8 @@ let {{ 'op2Suffix': op2Suffix, 'op2Index': '(i * sizeof(Element)) / 8' if wideop else 'i' } - iop = InstObjParams(name, 'Sve' + Name, 'SveIntCmpOp', - { + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveIntCmpOp', + { 'code': code, 'op_class': opClass, 'op2IsWide': 'true' if wideop else 'false', @@ -2226,8 +2226,8 @@ let {{ destPred.noneActive(tmpPred, eCount); CondCodesC = !destPred.lastActive(tmpPred, eCount); CondCodesV = 0;'''%{'op': op} - iop = InstObjParams(name, 'Sve' + Name, 'SveIntCmpImmOp', - {'code': code, 'op_class': opClass,}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveIntCmpImmOp', + {'code': code, 'op_class': opClass,}, []) iop.snippets['code'] = extraPrologCode + iop.snippets['code'] header_output += SveIntCmpImmOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) @@ -2274,7 +2274,7 @@ let {{ %(op)s; XDest = destElem; '''%{'op': op, 'dstType': dstType} - iop = InstObjParams(name, 'Sve' + Name, 'SveElemCountOp', + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveElemCountOp', {'code': code, 'op_class': opClass, 'dstIsVec': destType, 'dstIs32b': 'true' if dstIs32b else 'false'}, []) header_output += SveElemCountOpDeclare.subst(iop) @@ -2328,10 +2328,11 @@ let {{ CondCodesV = 0;''' extraPrologCode += ''' auto& destPred = PDest;''' - iop = InstObjParams(name, 'Sve' + Name, 'SvePartBrkOp', - {'code': code, 'op_class': opClass, - 'isMerging': 'true' if predType == PredType.MERGE - else 'false'}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, 'SvePartBrkOp', + {'code': code, 'op_class': opClass, + 'isMerging': + 'true' if predType == PredType.MERGE + else 'false'}, []) iop.snippets['code'] = extraPrologCode + iop.snippets['code'] header_output += SvePartBrkOpDeclare.subst(iop) exec_output += SveNonTemplatedOpExecute.subst(iop) @@ -2372,8 +2373,8 @@ let {{ CondCodesV = 0;''' extraPrologCode += ''' auto& destPred = PDest;''' - iop = InstObjParams(name, 'Sve' + Name, 'SvePartBrkPropOp', - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, 'SvePartBrkPropOp', + {'code': code, 'op_class': opClass}, []) iop.snippets['code'] = extraPrologCode + iop.snippets['code'] header_output += SvePartBrkPropOpDeclare.subst(iop) exec_output += SveNonTemplatedOpExecute.subst(iop) @@ -2406,8 +2407,8 @@ let {{ CondCodesV = 0;''' extraPrologCode += ''' auto& destPred = PDest;''' - iop = InstObjParams(name, 'Sve' + Name, 'SvePartBrkPropOp', - {'code': code, 'op_class': opClass}, []) + iop = ArmInstObjParams(name, 'Sve' + Name, 'SvePartBrkPropOp', + {'code': code, 'op_class': opClass}, []) iop.snippets['code'] = extraPrologCode + iop.snippets['code'] header_output += SvePartBrkPropOpDeclare.subst(iop) exec_output += SveNonTemplatedOpExecute.subst(iop) @@ -2467,15 +2468,15 @@ let {{ AA64FpDest_x[i] = (Element)0x0; } ''' - iop = InstObjParams(name, 'Sve' + Name, 'SveSelectOp', - {'code': code, 'op_class': opClass, - 'isCond': 'true' if isCond else 'false', - 'isScalar': 'true' - if destType == DstRegType.Scalar else 'false', - 'isSimdFp': 'true' - if destType == DstRegType.SimdFpScalar - else 'false'}, - []) + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveSelectOp', + {'code': code, 'op_class': opClass, + 'isCond': 'true' if isCond else 'false', + 'isScalar': 'true' + if destType == DstRegType.Scalar else 'false', + 'isSimdFp': 'true' + if destType == DstRegType.SimdFpScalar + else 'false'}, + []) header_output += SveSelectOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) for type in types: @@ -2515,7 +2516,7 @@ let {{ CondCodesV = 0;''' extraPrologCode = ''' auto& destPred = PDest;''' - iop = InstObjParams(name, 'Sve' + Name, 'SveUnaryPredPredOp', + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveUnaryPredPredOp', {'code': code, 'op_class': opClass}, []) iop.snippets['code'] = extraPrologCode + iop.snippets['code'] header_output += SveUnaryPredOpDeclare.subst(iop) @@ -2554,7 +2555,7 @@ let {{ CondCodesV = 0;''' extraPrologCode = ''' auto& destPred = PDest;''' - iop = InstObjParams(name, 'Sve' + Name, 'SveUnaryPredPredOp', + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveUnaryPredPredOp', {'code': code, 'op_class': opClass}, []) iop.snippets['code'] = extraPrologCode + iop.snippets['code'] header_output += SveUnaryPredOpDeclare.subst(iop) @@ -2579,7 +2580,7 @@ let {{ } AA64FpDest_x[i] = val; }''' - iop = InstObjParams(name, 'Sve' + Name, 'SveTblOp', + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveTblOp', {'code': code, 'op_class': opClass}, []) header_output += SveBinUnpredOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) @@ -2636,7 +2637,7 @@ let {{ code += ''' } ''' - iop = InstObjParams(name, 'Sve' + Name, 'SveUnpackOp', + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveUnpackOp', {'code': code, 'op_class': opClass}, []) if regType == SrcRegType.Predicate: iop.snippets['code'] = extraPrologCode + iop.snippets['code'] @@ -2657,7 +2658,7 @@ let {{ POp1_ub.noneActive(GpOp_ub, eCount); CondCodesC = !POp1_ub.lastActive(GpOp_ub, eCount); CondCodesV = 0;''' - iop = InstObjParams(name, 'Sve' + Name, 'SvePredTestOp', + iop = ArmInstObjParams(name, 'Sve' + Name, 'SvePredTestOp', {'code': code, 'op_class': opClass}, []) header_output += SvePredicateTestOpDeclare.subst(iop) exec_output += SveNonTemplatedOpExecute.subst(iop) @@ -2681,7 +2682,7 @@ let {{ x++; } }''' - iop = InstObjParams(name, 'Sve' + Name, 'SveUnaryPredOp', + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveUnaryPredOp', {'code': code, 'op_class': opClass}, []) header_output += SveUnaryPredOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) @@ -2705,7 +2706,7 @@ let {{ M5_VAR_USED auto& destPred = PDest;''' baseClass = ('SvePredUnaryWImplicitSrcOp' if predType == PredType.NONE else 'SvePredUnaryWImplicitSrcPredOp') - iop = InstObjParams(name, 'Sve' + Name, baseClass, + iop = ArmInstObjParams(name, 'Sve' + Name, baseClass, {'code': code, 'op_class': opClass}, []) iop.snippets['code'] = extraPrologCode + iop.snippets['code'] if predType == PredType.NONE: @@ -2724,7 +2725,7 @@ let {{ M5_VAR_USED auto& destPred = Ffr;''' baseClass = ('SveWImplicitSrcDstOp' if isSetFfr else 'SvePredUnaryWImplicitDstOp') - iop = InstObjParams(name, 'Sve' + Name, baseClass, + iop = ArmInstObjParams(name, 'Sve' + Name, baseClass, {'code': code, 'op_class': opClass}, []) iop.snippets['code'] = extraPrologCode + iop.snippets['code'] if isSetFfr: @@ -2755,7 +2756,7 @@ let {{ AA64FpDest_x[i] = auxOp1[pos-eCount]; } ''' - iop = InstObjParams(name, 'Sve' + Name, 'SveBinImmUnpredDestrOp', + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveBinImmUnpredDestrOp', {'code': code, 'op_class': opClass}, []) header_output += SveBinImmUnpredOpDeclare.subst(iop); exec_output += SveOpExecute.subst(iop) @@ -2791,7 +2792,7 @@ let {{ AA64FpDest_x[i] = auxDest[i]; } ''' - iop = InstObjParams(name, 'Sve' + Name, 'SveBinDestrPredOp', + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveBinDestrPredOp', {'code': code, 'op_class': opClass}, []) header_output += SveBinDestrPredOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) @@ -2812,7 +2813,7 @@ let {{ for (int i = 0; i < eCount; ++i) { AA64FpDest_x[i] = srcElem1; }''' - iop = InstObjParams(name, 'Sve' + Name, 'SveBinImmIdxUnpredOp', + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveBinImmIdxUnpredOp', {'code': code, 'op_class': opClass}, []) header_output += SveBinImmUnpredOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) @@ -2856,7 +2857,7 @@ let {{ destPred.set_raw(i, auxPOp1.get_raw(eCount - i - 1));''' code += ''' }''' - iop = InstObjParams(name, 'Sve' + Name, 'SveUnaryUnpredOp', + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveUnaryUnpredOp', {'code': code, 'op_class': opClass}, []) if srcType == SrcRegType.Predicate: iop.snippets['code'] = extraPrologCode + iop.snippets['code'] @@ -2885,7 +2886,7 @@ let {{ AA64FpDest_x[i] = AA64FpDestMerge_x[i-1]; } AA64FpDest_x[0] = srcElem1;''' - iop = InstObjParams(name, 'Sve' + Name, 'SveUnarySca2VecUnpredOp', + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveUnarySca2VecUnpredOp', {'code': code, 'op_class': opClass, 'isSimdFp': 'true' if srcType == SrcRegType.SimdFpScalar else 'false'}, []) @@ -2922,7 +2923,7 @@ let {{ } AA64FpDestMerge_xd[i] = res; }''' - iop = InstObjParams(name, 'Sve' + Name, + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveDotProdIdxOp' if isIndexed else 'SveDotProdOp', {'code': code, 'op_class': opClass}, []) @@ -2954,7 +2955,7 @@ let {{ AA64FpDest_x[i] = 0; } AA64FpDest_x[0] = destElem;'''%{'op': op} - iop = InstObjParams(name, 'Sve' + Name, 'SveOrdReducOp', + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveOrdReducOp', {'code': code, 'op_class': opClass}, []) header_output += SveReducOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) @@ -3001,7 +3002,7 @@ let {{ AA64FpDest_x[2 * i + 1] = acc_i; } ''' - iop = InstObjParams(name, 'Sve' + Name, 'SveComplexOp', + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveComplexOp', {'code': code, 'op_class': opClass}, []) header_output += SveComplexOpDeclare.subst(iop) exec_output += SveOpExecute.subst(iop) @@ -3081,7 +3082,7 @@ let {{ AA64FpDest_x[i] = auxDest[i]; } ''' - iop = InstObjParams(name, 'Sve' + Name, + iop = ArmInstObjParams(name, 'Sve' + Name, 'SveComplexIdxOp' if predType == PredType.NONE else 'SveComplexOp', {'code': code, 'op_class': opClass}, []) @@ -4117,7 +4118,7 @@ let {{ xc->tcBase()); XDest = eCount * (int64_t) imm; ''' - rdvlIop = InstObjParams('rdvl', 'SveRdvl', 'RegImmOp', rdvlCode, []) + rdvlIop = ArmInstObjParams('rdvl', 'SveRdvl', 'RegImmOp', rdvlCode, []) header_output += RegImmOpDeclare.subst(rdvlIop) decoder_output += RegImmOpConstructor.subst(rdvlIop) exec_output += BasicExecute.subst(rdvlIop) diff --git a/src/arch/arm/isa/insts/sve_mem.isa b/src/arch/arm/isa/insts/sve_mem.isa index 8599900f4..213f57d65 100644 --- a/src/arch/arm/isa/insts/sve_mem.isa +++ b/src/arch/arm/isa/insts/sve_mem.isa @@ -813,7 +813,7 @@ let {{ storeWrEnableCode = ''' auto wrEn = std::vector(sizeof(MemElemType) * eCount, true); ''' - loadIop = InstObjParams('ldr', + loadIop = ArmInstObjParams('ldr', 'SveLdrPred' if isPred else 'SveLdrVec', 'SveMemPredFillSpill' if isPred else 'SveMemVecFillSpill', {'tpl_header': '', @@ -824,7 +824,7 @@ let {{ 'fault_code' : '', 'fa_code' : ''}, ['IsLoad']) - storeIop = InstObjParams('str', + storeIop = ArmInstObjParams('str', 'SveStrPred' if isPred else 'SveStrVec', 'SveMemPredFillSpill' if isPred else 'SveMemVecFillSpill', {'tpl_header': '', @@ -997,7 +997,7 @@ let {{ } ''' % ('' if firstFaulting else nonFaultingCode) - loadIop = InstObjParams('ld1', + loadIop = ArmInstObjParams('ld1', 'SveContigLoadSI' if offsetIsImm else 'SveContigLoadSS', 'SveContigMemSI' if offsetIsImm else 'SveContigMemSS', {'tpl_header': tplHeader, @@ -1008,7 +1008,7 @@ let {{ 'fault_code' : '', 'fa_code' : ''}, ['IsLoad']) - storeIop = InstObjParams('st1', + storeIop = ArmInstObjParams('st1', 'SveContigStoreSI' if offsetIsImm else 'SveContigStoreSS', 'SveContigMemSI' if offsetIsImm else 'SveContigMemSS', {'tpl_header': tplHeader, @@ -1018,7 +1018,7 @@ let {{ 'ea_code' : sveEnabledCheckCode + eaCode, 'fa_code' : ''}, ['IsStore']) - faultIop = InstObjParams('ldff1' if firstFaulting else 'ldnf1', + faultIop = ArmInstObjParams('ldff1' if firstFaulting else 'ldnf1', 'SveContigFFLoadSS' if firstFaulting else 'SveContigNFLoadSI', 'SveContigMemSS' if firstFaulting else 'SveContigMemSI', {'tpl_header': tplHeader, @@ -1083,7 +1083,7 @@ let {{ } } ''' - iop = InstObjParams('ld1r', + iop = ArmInstObjParams('ld1r', 'SveLoadAndRepl', 'SveContigMemSI', {'tpl_header': tplHeader, @@ -1145,7 +1145,7 @@ let {{ predCheckCode = 'GpOp_x[index]' faultStatusSetCode = 'PUreg0_x[elemIndex] = 1;' faultStatusResetCode = 'PUreg0_x[elemIndex] = 0;' - loadIop = InstObjParams('ld1', + loadIop = ArmInstObjParams('ld1', ('SveGatherLoadVIMicroop' if indexed_addr_form == IndexedAddrForm.VEC_PLUS_IMM else 'SveGatherLoadSVMicroop'), @@ -1159,7 +1159,7 @@ let {{ 'pred_check_code' : predCheckCode, 'fa_code' : ''}, ['IsMicroop', 'IsLoad']) - storeIop = InstObjParams('st1', + storeIop = ArmInstObjParams('st1', ('SveScatterStoreVIMicroop' if indexed_addr_form == IndexedAddrForm.VEC_PLUS_IMM else 'SveScatterStoreSVMicroop'), @@ -1220,7 +1220,7 @@ let {{ Ffr_ub[index * sizeof(RegElemType) + j] = FfrAux_x[index]; } ''' - iop = InstObjParams('ldff1', + iop = ArmInstObjParams('ldff1', 'SveFirstFaultWritebackMicroop', 'MicroOp', {'tpl_header': tplHeader, @@ -1246,7 +1246,7 @@ let {{ for (unsigned i = 0; i < eCount; i++) { AA64FpUreg0_ub[i] = AA64FpOp1_ub[i]; }''' - iop = InstObjParams('ld1', + iop = ArmInstObjParams('ld1', 'SveGatherLoadCpySrcVecMicroop', 'MicroOp', {'code': code}, @@ -1301,17 +1301,17 @@ let {{ AA64FpDest_x[i] = AA64FpOp1V3S_x[srcIdx]; }''' - iop2 = InstObjParams('intrlv', + iop2 = ArmInstObjParams('intrlv', 'SveIntrlv2Microop', 'MicroOp', {'code': code2}, ['IsMicroop']) - iop3 = InstObjParams('intrlv', + iop3 = ArmInstObjParams('intrlv', 'SveIntrlv3Microop', 'MicroOp', {'code': code3}, ['IsMicroop']) - iop4 = InstObjParams('intrlv', + iop4 = ArmInstObjParams('intrlv', 'SveIntrlv4Microop', 'MicroOp', {'code': code4}, @@ -1375,17 +1375,17 @@ let {{ AA64FpDest_x[i] = AA64IntrlvReg3_x[srcIdx]; }''' - iop2 = InstObjParams('deintrlv', + iop2 = ArmInstObjParams('deintrlv', 'SveDeIntrlv2Microop', 'MicroOp', {'code': code2}, ['IsMicroop']) - iop3 = InstObjParams('deintrlv', + iop3 = ArmInstObjParams('deintrlv', 'SveDeIntrlv3Microop', 'MicroOp', {'code': code3}, ['IsMicroop']) - iop4 = InstObjParams('deintrlv', + iop4 = ArmInstObjParams('deintrlv', 'SveDeIntrlv4Microop', 'MicroOp', {'code': code4}, @@ -1438,7 +1438,7 @@ let {{ storeWrEnableCode = ''' auto wrEn = std::vector(sizeof(Element) * eCount, true); ''' - loadIop = InstObjParams('ldxx', + loadIop = ArmInstObjParams('ldxx', 'SveLoadRegImmMicroop' if offsetIsImm else 'SveLoadRegRegMicroop', 'MicroOp', {'targs': 'Element', @@ -1446,7 +1446,7 @@ let {{ 'ea_code' : sveEnabledCheckCode + eaCode, 'fa_code' : ''}, ['IsLoad', 'IsMicroop']) - storeIop = InstObjParams('stxx', + storeIop = ArmInstObjParams('stxx', 'SveStoreRegImmMicroop' if offsetIsImm else 'SveStoreRegRegMicroop', 'MicroOp', @@ -1518,7 +1518,7 @@ let {{ AA64FpDest_uq[i] = qword; } ''' - iop = InstObjParams('ld1rq', + iop = ArmInstObjParams('ld1rq', 'SveLd1RqSI' if offsetIsImm else 'SveLd1RqSS', 'SveContigMemSI' if offsetIsImm else 'SveContigMemSS', {'tpl_header': tplHeader, diff --git a/src/arch/arm/isa/main.isa b/src/arch/arm/isa/main.isa index aa52baeb6..e34ed382a 100644 --- a/src/arch/arm/isa/main.isa +++ b/src/arch/arm/isa/main.isa @@ -54,6 +54,8 @@ // namespace ArmISA; +##include "arminstobjparams.isa" + //Include the bitfield definitions ##include "bitfields.isa" diff --git a/src/arch/arm/isa/templates/basic.isa b/src/arch/arm/isa/templates/basic.isa index 956f5cdc1..d0bc82da2 100644 --- a/src/arch/arm/isa/templates/basic.isa +++ b/src/arch/arm/isa/templates/basic.isa @@ -45,6 +45,9 @@ def template BasicDeclare {{ */ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst); @@ -57,6 +60,7 @@ def template BasicConstructor {{ %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -70,6 +74,7 @@ def template BasicConstructor64 {{ %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa index e1dcd2f70..3bb9e6b2b 100644 --- a/src/arch/arm/isa/templates/branch.isa +++ b/src/arch/arm/isa/templates/branch.isa @@ -38,6 +38,9 @@ def template BranchImmCondDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, int32_t _imm, @@ -56,6 +59,7 @@ def template BranchImmCondConstructor {{ ConditionCode _condCode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _condCode) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -71,6 +75,9 @@ def template BranchImmCondConstructor {{ def template BranchRegCondDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, @@ -84,6 +91,7 @@ def template BranchRegCondConstructor {{ ConditionCode _condCode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _condCode) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -101,6 +109,9 @@ def template BranchRegCondConstructor {{ def template BranchTableDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2); @@ -116,6 +127,7 @@ def template BranchRegRegConstructor {{ IntRegIndex _op1, IntRegIndex _op2) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -131,6 +143,9 @@ def template BranchRegRegConstructor {{ def template BranchImmRegDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, int32_t imm, IntRegIndex _op1); @@ -150,6 +165,7 @@ def template BranchImmRegConstructor {{ IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) { + %(set_reg_idx_arr)s; %(constructor)s; flags[IsCondControl] = true; } diff --git a/src/arch/arm/isa/templates/branch64.isa b/src/arch/arm/isa/templates/branch64.isa index 7d3a9ac95..5b386755d 100644 --- a/src/arch/arm/isa/templates/branch64.isa +++ b/src/arch/arm/isa/templates/branch64.isa @@ -38,6 +38,9 @@ def template BranchImm64Declare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, int64_t _imm); @@ -49,6 +52,7 @@ def template BranchImm64Constructor {{ %(class_name)s::%(class_name)s(ExtMachInst machInst, int64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -56,6 +60,9 @@ def template BranchImm64Constructor {{ def template BranchImmCond64Declare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, int64_t _imm, @@ -69,6 +76,7 @@ def template BranchImmCond64Constructor {{ ExtMachInst machInst, int64_t _imm, ConditionCode _condCode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _condCode) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -76,6 +84,9 @@ def template BranchImmCond64Constructor {{ def template BranchReg64Declare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1); @@ -87,6 +98,7 @@ def template BranchReg64Constructor {{ %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -94,6 +106,9 @@ def template BranchReg64Constructor {{ def template BranchRegReg64Declare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2); @@ -106,6 +121,7 @@ def template BranchRegReg64Constructor {{ IntRegIndex _op2) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -113,6 +129,9 @@ def template BranchRegReg64Constructor {{ def template BranchImmReg64Declare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, int64_t imm, IntRegIndex _op1); @@ -125,6 +144,7 @@ def template BranchImmReg64Constructor {{ IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -132,6 +152,9 @@ def template BranchImmReg64Constructor {{ def template BranchImmImmReg64Declare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, int64_t _imm1, int64_t _imm2, @@ -147,6 +170,7 @@ def template BranchImmImmReg64Constructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm1, _imm2, _op1) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; diff --git a/src/arch/arm/isa/templates/data64.isa b/src/arch/arm/isa/templates/data64.isa index 0da27cd05..2b1e8c45c 100644 --- a/src/arch/arm/isa/templates/data64.isa +++ b/src/arch/arm/isa/templates/data64.isa @@ -38,6 +38,9 @@ def template DataXImmDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, @@ -53,6 +56,7 @@ def template DataXImmConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -60,6 +64,9 @@ def template DataXImmConstructor {{ def template DataXSRegDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, @@ -77,6 +84,7 @@ def template DataXSRegConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _shiftAmt, _shiftType) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -84,6 +92,9 @@ def template DataXSRegConstructor {{ def template DataXERegDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, @@ -101,6 +112,7 @@ def template DataXERegConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _extendType, _shiftAmt) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -108,6 +120,9 @@ def template DataXERegConstructor {{ def template DataX1RegDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1); @@ -120,6 +135,7 @@ def template DataX1RegConstructor {{ IntRegIndex _dest, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -127,6 +143,9 @@ def template DataX1RegConstructor {{ def template DataX2RegDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, @@ -141,6 +160,7 @@ def template DataX2RegConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -148,6 +168,9 @@ def template DataX2RegConstructor {{ def template DataX2RegImmDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, @@ -163,6 +186,7 @@ def template DataX2RegImmConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -170,6 +194,9 @@ def template DataX2RegImmConstructor {{ def template DataX3RegDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, @@ -185,6 +212,7 @@ def template DataX3RegConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _op3) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -192,6 +220,9 @@ def template DataX3RegConstructor {{ def template DataXCondCompImmDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, @@ -207,6 +238,7 @@ def template DataXCondCompImmConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _imm, _condCode, _defCc) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -214,6 +246,9 @@ def template DataXCondCompImmConstructor {{ def template DataXCondCompRegDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, @@ -229,6 +264,7 @@ def template DataXCondCompRegConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2, _condCode, _defCc) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -236,6 +272,9 @@ def template DataXCondCompRegConstructor {{ def template DataXCondSelDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, @@ -252,6 +291,7 @@ def template DataXCondSelConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _condCode) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; diff --git a/src/arch/arm/isa/templates/macromem.isa b/src/arch/arm/isa/templates/macromem.isa index d851f464f..094158a5d 100644 --- a/src/arch/arm/isa/templates/macromem.isa +++ b/src/arch/arm/isa/templates/macromem.isa @@ -46,6 +46,9 @@ def template MicroMemDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, bool _up, @@ -66,6 +69,7 @@ def template MicroMemConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _ura, _urb, _up, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -79,6 +83,9 @@ def template MicroMemConstructor {{ def template MicroMemPairDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst, RegIndex _dreg1, RegIndex _dreg2, RegIndex _base, @@ -100,6 +107,7 @@ def template MicroMemPairConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dreg1, _dreg2, _base, _up, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -118,6 +126,9 @@ def template MicroNeonMemDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) : @@ -125,6 +136,7 @@ def template MicroNeonMemDeclare {{ %(op_class)s, _dest, _ura, _imm) { memAccessFlags |= extraMemFlags; + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -149,6 +161,9 @@ def template MicroNeonMemDeclare {{ def template MicroSetPCCPSRDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst, IntRegIndex _ura, @@ -166,6 +181,7 @@ def template MicroSetPCCPSRConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _ura, _urb, _urc) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { flags[IsCondControl] = true; @@ -210,12 +226,16 @@ def template MicroNeonMixDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, uint8_t _step) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _step) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -261,12 +281,16 @@ def template MicroNeonMixLaneDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, uint8_t _step, unsigned _lane) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _step, _lane) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -287,6 +311,9 @@ def template MicroNeonMixLaneDeclare {{ def template MicroIntMovDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb); @@ -300,6 +327,7 @@ def template MicroIntMovConstructor {{ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _ura, _urb) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -317,6 +345,9 @@ def template MicroIntMovConstructor {{ def template MicroIntImmDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, @@ -333,6 +364,7 @@ def template MicroIntImmConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _ura, _urb, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -350,6 +382,7 @@ def template MicroIntImmXConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _ura, _urb, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -357,6 +390,9 @@ def template MicroIntImmXConstructor {{ def template MicroIntRegDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, RegIndex _urc, @@ -372,6 +408,7 @@ def template MicroIntXERegConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _ura, _urb, _urc, _type, _shiftAmt) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -379,6 +416,9 @@ def template MicroIntXERegConstructor {{ def template MicroIntXERegDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, RegIndex _urc, @@ -395,6 +435,7 @@ def template MicroIntRegConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _ura, _urb, _urc, _shiftAmt, _shiftType) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -415,6 +456,9 @@ def template MacroMemDeclare {{ */ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex rn, bool index, bool up, @@ -429,6 +473,7 @@ def template MacroMemConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, index, up, user, writeback, load, reglist) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -442,6 +487,9 @@ def template MacroMemConstructor {{ def template BigFpMemImmDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(const char *mnemonic, ExtMachInst machInst, @@ -454,6 +502,7 @@ def template BigFpMemImmConstructor {{ bool load, IntRegIndex dest, IntRegIndex base, int64_t imm) : %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, imm) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -461,6 +510,9 @@ def template BigFpMemImmConstructor {{ def template BigFpMemRegDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(const char *mnemonic, ExtMachInst machInst, @@ -476,6 +528,7 @@ def template BigFpMemRegConstructor {{ %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, offset, type, imm) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -483,6 +536,9 @@ def template BigFpMemRegConstructor {{ def template BigFpMemLitDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(const char *mnemonic, ExtMachInst machInst, @@ -495,6 +551,7 @@ def template BigFpMemLitConstructor {{ IntRegIndex dest, int64_t imm) : %(base_class)s(mnemonic, machInst, %(op_class)s, dest, imm) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -502,6 +559,9 @@ def template BigFpMemLitConstructor {{ def template PairMemDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(const char *mnemonic, ExtMachInst machInst, @@ -521,6 +581,7 @@ def template PairMemConstructor {{ fp, load, noAlloc, signExt, exclusive, acrel, imm, mode, rn, rt, rt2) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -528,6 +589,9 @@ def template PairMemConstructor {{ def template VMemMultDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, unsigned width, @@ -543,6 +607,7 @@ def template VMemMultConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width, rn, vd, regs, inc, size, align, rm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -555,6 +620,9 @@ def template VMemMultConstructor {{ def template VMemSingleDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, bool all, unsigned width, @@ -570,6 +638,7 @@ def template VMemSingleConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width, rn, vd, regs, inc, size, align, rm, lane) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -585,6 +654,9 @@ def template MacroVFPMemDeclare {{ */ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex rn, @@ -600,6 +672,7 @@ def template MacroVFPMemConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, vd, single, up, writeback, load, offset) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index f83dca61a..ca9e25a9c 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -588,8 +588,10 @@ def template RfeDeclare {{ */ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, uint32_t _base, int _mode, bool _wb); @@ -607,8 +609,10 @@ def template SrsDeclare {{ */ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, uint32_t _regMode, int _mode, bool _wb); @@ -626,8 +630,10 @@ def template SwapDeclare {{ */ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _op1, uint32_t _base); @@ -645,8 +651,10 @@ def template LoadStoreDImmDeclare {{ */ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _dest2, @@ -665,8 +673,10 @@ def template StoreExDImmDeclare {{ */ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, uint32_t _result, uint32_t _dest, uint32_t _dest2, @@ -685,8 +695,10 @@ def template LoadStoreImmDeclare {{ */ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); @@ -710,8 +722,10 @@ def template StoreExImmDeclare {{ */ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, uint32_t _result, uint32_t _dest, uint32_t _base, @@ -730,8 +744,10 @@ def template StoreDRegDeclare {{ */ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _dest2, @@ -752,8 +768,10 @@ def template StoreRegDeclare {{ */ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, @@ -779,8 +797,10 @@ def template LoadDRegDeclare {{ */ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _dest2, @@ -801,8 +821,10 @@ def template LoadRegDeclare {{ */ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, @@ -828,8 +850,10 @@ def template LoadImmDeclare {{ */ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); @@ -853,6 +877,7 @@ def template RfeConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (IntRegIndex)_base, (AddrMode)_mode, _wb) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -883,6 +908,7 @@ def template SrsConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (OperatingMode)_regMode, (AddrMode)_mode, _wb) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -907,6 +933,7 @@ def template SwapConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -924,6 +951,7 @@ def template LoadStoreDImmConstructor {{ (IntRegIndex)_dest, (IntRegIndex)_dest2, (IntRegIndex)_base, _add, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -950,6 +978,7 @@ def template StoreExDImmConstructor {{ (IntRegIndex)_result, (IntRegIndex)_dest, (IntRegIndex)_dest2, (IntRegIndex)_base, _add, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -975,6 +1004,7 @@ def template LoadStoreImmConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -1001,6 +1031,7 @@ def template StoreExImmConstructor {{ (IntRegIndex)_result, (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -1030,6 +1061,7 @@ def template StoreDRegConstructor {{ _shiftAmt, (ArmShiftType)_shiftType, (IntRegIndex)_index) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -1058,6 +1090,7 @@ def template StoreRegConstructor {{ _shiftAmt, (ArmShiftType)_shiftType, (IntRegIndex)_index) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -1087,6 +1120,7 @@ def template LoadDRegConstructor {{ _shiftAmt, (ArmShiftType)_shiftType, (IntRegIndex)_index) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -1128,6 +1162,7 @@ def template LoadRegConstructor {{ _shiftAmt, (ArmShiftType)_shiftType, (IntRegIndex)_index) { + %(set_reg_idx_arr)s; %(constructor)s; M5_VAR_USED bool conditional = false; if (!(condCode == COND_AL || condCode == COND_UC)) { @@ -1194,6 +1229,7 @@ def template LoadImmConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; M5_VAR_USED bool conditional = false; if (!(condCode == COND_AL || condCode == COND_UC)) { diff --git a/src/arch/arm/isa/templates/mem64.isa b/src/arch/arm/isa/templates/mem64.isa index ffc28c4f3..f7034e684 100644 --- a/src/arch/arm/isa/templates/mem64.isa +++ b/src/arch/arm/isa/templates/mem64.isa @@ -285,8 +285,10 @@ def template StoreEx64CompleteAcc {{ def template DCStore64Declare {{ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, IntRegIndex _base, MiscRegIndex _dest, uint64_t _imm); @@ -310,6 +312,7 @@ def template DCStore64Constructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _base, _dest, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; assert(!%(use_uops)d); } @@ -376,8 +379,10 @@ def template DCStore64InitiateAcc {{ def template LoadStoreImm64Declare {{ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _base, int64_t _imm); @@ -398,8 +403,10 @@ def template LoadStoreImm64Declare {{ def template LoadStoreImmU64Declare {{ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _base, int64_t _imm, @@ -422,8 +429,10 @@ def template LoadStoreImmU64Declare {{ def template LoadStoreImmDU64Declare {{ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, @@ -449,8 +458,10 @@ def template StoreImmDEx64Declare {{ */ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, @@ -467,8 +478,10 @@ def template StoreImmDEx64Declare {{ def template LoadStoreReg64Declare {{ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset, @@ -490,8 +503,10 @@ def template LoadStoreReg64Declare {{ def template LoadStoreRegU64Declare {{ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset, @@ -515,8 +530,10 @@ def template LoadStoreRegU64Declare {{ def template LoadStoreRaw64Declare {{ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _base); @@ -537,8 +554,10 @@ def template LoadStoreRaw64Declare {{ def template LoadStoreEx64Declare {{ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result); @@ -559,8 +578,10 @@ def template LoadStoreEx64Declare {{ def template LoadStoreLit64Declare {{ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, int64_t _imm); @@ -580,8 +601,10 @@ def template LoadStoreLit64Declare {{ def template LoadStoreLitU64Declare {{ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, int64_t _imm, bool noAlloc = false, bool exclusive = false, @@ -606,6 +629,7 @@ def template LoadStoreImm64Constructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (IntRegIndex)_dest, (IntRegIndex)_base, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; #if %(use_uops)d assert(numMicroops >= 2); @@ -626,6 +650,7 @@ def template LoadStoreImmU64Constructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _base, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; assert(!%(use_uops)d); setExcAcRel(exclusive, acrel); @@ -639,6 +664,7 @@ def template LoadStoreImmDU64Constructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _dest2, _base, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; assert(!%(use_uops)d); setExcAcRel(exclusive, acrel); @@ -652,6 +678,7 @@ def template StoreImmDEx64Constructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _result, _dest, _dest2, _base, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; assert(!%(use_uops)d); } @@ -665,6 +692,7 @@ def template LoadStoreReg64Constructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _base, _offset, _type, _shiftAmt) { + %(set_reg_idx_arr)s; %(constructor)s; #if %(use_uops)d assert(numMicroops >= 2); @@ -687,6 +715,7 @@ def template LoadStoreRegU64Constructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _base, _offset, _type, _shiftAmt) { + %(set_reg_idx_arr)s; %(constructor)s; assert(!%(use_uops)d); setExcAcRel(exclusive, acrel); @@ -698,6 +727,7 @@ def template LoadStoreRaw64Constructor {{ IntRegIndex _dest, IntRegIndex _base) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _base) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -708,6 +738,7 @@ def template LoadStoreEx64Constructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _base, _result) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -718,6 +749,7 @@ def template LoadStoreLit64Constructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (IntRegIndex)_dest, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; #if %(use_uops)d assert(numMicroops >= 2); @@ -738,6 +770,7 @@ def template LoadStoreLitU64Constructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (IntRegIndex)_dest, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; assert(!%(use_uops)d); setExcAcRel(exclusive, acrel); @@ -821,8 +854,10 @@ def template AmoOpCompleteAcc {{ def template AmoOpDeclare {{ class %(class_name)s : public %(base_class)s { - public: + private: + %(reg_idx_arr_decl)s; + public: /// Constructor. %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result); @@ -847,6 +882,7 @@ def template AmoOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _base, _result) { + %(set_reg_idx_arr)s; %(constructor)s; flags[IsStore] = false; flags[IsLoad] = false; @@ -856,6 +892,9 @@ def template AmoOpConstructor {{ def template AmoPairOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: uint32_t d2_src ; uint32_t r2_src ; @@ -884,6 +923,7 @@ def template AmoPairOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _base, _result) { + %(set_reg_idx_arr)s; %(constructor)s; uint32_t d2 = RegId(IntRegClass, dest).index() + 1 ; @@ -903,6 +943,9 @@ def template AmoPairOpConstructor {{ def template AmoArithmeticOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: bool isXZR ; /// Constructor. @@ -928,6 +971,7 @@ def template AmoArithmeticOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _base, _result) { + %(set_reg_idx_arr)s; %(constructor)s; isXZR = false; uint32_t r2 = RegId(IntRegClass, dest).index() ; diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa index f653401b8..3d3393dc7 100644 --- a/src/arch/arm/isa/templates/misc.isa +++ b/src/arch/arm/isa/templates/misc.isa @@ -38,6 +38,9 @@ def template MrsDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest); @@ -49,6 +52,7 @@ def template MrsConstructor {{ %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -61,6 +65,9 @@ def template MrsConstructor {{ def template MrsBankedRegDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: uint8_t byteMask; bool r; @@ -79,6 +86,7 @@ def template MrsBankedRegConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest), byteMask(_sysM), r(_r) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -91,6 +99,9 @@ def template MrsBankedRegConstructor {{ def template MsrBankedRegDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: bool r; @@ -108,6 +119,7 @@ def template MsrBankedRegConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _sysM), r(_r) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -120,6 +132,9 @@ def template MsrBankedRegConstructor {{ def template MsrRegDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask); @@ -132,6 +147,7 @@ def template MsrRegConstructor {{ uint8_t mask) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -144,6 +160,9 @@ def template MsrRegConstructor {{ def template MsrImmDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask); @@ -156,6 +175,7 @@ def template MsrImmConstructor {{ uint8_t mask) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -168,6 +188,9 @@ def template MsrImmConstructor {{ def template MrrcOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, MiscRegIndex _op1, @@ -183,6 +206,7 @@ def template MrrcOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, op1, dest, dest2, imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -195,6 +219,9 @@ def template MrrcOpConstructor {{ def template McrrOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2, @@ -210,6 +237,7 @@ def template McrrOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, op1, op2, dest, imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -222,6 +250,9 @@ def template McrrOpConstructor {{ def template ImmOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, uint64_t _imm); @@ -233,6 +264,7 @@ def template ImmOpConstructor {{ %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -245,6 +277,9 @@ def template ImmOpConstructor {{ def template RegImmOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm); @@ -257,6 +292,7 @@ def template RegImmOpConstructor {{ IntRegIndex _dest, uint64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -269,6 +305,9 @@ def template RegImmOpConstructor {{ def template RegRegOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1); @@ -281,6 +320,7 @@ def template RegRegOpConstructor {{ IntRegIndex _dest, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -293,6 +333,9 @@ def template RegRegOpConstructor {{ def template RegRegRegImmOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, @@ -308,6 +351,7 @@ def template RegRegRegImmOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -320,6 +364,9 @@ def template RegRegRegImmOpConstructor {{ def template RegRegRegRegOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, @@ -335,6 +382,7 @@ def template RegRegRegRegOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _op3) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -347,6 +395,9 @@ def template RegRegRegRegOpConstructor {{ def template RegRegRegOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, @@ -361,6 +412,7 @@ def template RegRegRegOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -373,6 +425,9 @@ def template RegRegRegOpConstructor {{ def template RegRegImmOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, @@ -387,6 +442,7 @@ def template RegRegImmOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -399,6 +455,9 @@ def template RegRegImmOpConstructor {{ def template MiscRegRegImmOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, IntRegIndex _op1, @@ -413,6 +472,7 @@ def template MiscRegRegImmOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -425,6 +485,9 @@ def template MiscRegRegImmOpConstructor {{ def template RegMiscRegImmOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, MiscRegIndex _op1, @@ -439,6 +502,7 @@ def template RegMiscRegImmOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -451,6 +515,9 @@ def template RegMiscRegImmOpConstructor {{ def template RegImmImmOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, @@ -465,6 +532,7 @@ def template RegImmImmOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm1, _imm2) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -477,6 +545,9 @@ def template RegImmImmOpConstructor {{ def template RegRegImmImmOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, @@ -492,6 +563,7 @@ def template RegRegImmImmOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _imm1, _imm2) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -504,6 +576,9 @@ def template RegRegImmImmOpConstructor {{ def template RegImmRegOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, @@ -518,6 +593,7 @@ def template RegImmRegOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm, _op1) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -530,6 +606,9 @@ def template RegImmRegOpConstructor {{ def template RegImmRegShiftOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm, @@ -547,6 +626,7 @@ def template RegImmRegShiftOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm, _op1, _shiftAmt, _shiftType) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -559,6 +639,9 @@ def template RegImmRegShiftOpConstructor {{ def template MiscRegRegImmMemOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, diff --git a/src/arch/arm/isa/templates/misc64.isa b/src/arch/arm/isa/templates/misc64.isa index df7733d9d..faad3490c 100644 --- a/src/arch/arm/isa/templates/misc64.isa +++ b/src/arch/arm/isa/templates/misc64.isa @@ -38,6 +38,9 @@ def template ImmOp64Declare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst,uint64_t _imm); @@ -50,6 +53,7 @@ def template ImmOp64Constructor {{ %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -57,6 +61,9 @@ def template ImmOp64Constructor {{ def template RegRegImmImmOp64Declare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, @@ -73,6 +80,7 @@ def template RegRegImmImmOp64Constructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _imm1, _imm2) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -80,6 +88,9 @@ def template RegRegImmImmOp64Constructor {{ def template RegRegRegImmOp64Declare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, @@ -95,6 +106,7 @@ def template RegRegRegImmOp64Constructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -102,6 +114,9 @@ def template RegRegRegImmOp64Constructor {{ def template MiscRegOp64Declare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, uint64_t _imm); @@ -115,6 +130,7 @@ def template MiscRegOp64Constructor {{ uint64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -122,6 +138,9 @@ def template MiscRegOp64Constructor {{ def template MiscRegRegOp64Declare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, @@ -137,6 +156,7 @@ def template MiscRegRegOp64Constructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -144,6 +164,9 @@ def template MiscRegRegOp64Constructor {{ def template RegMiscRegOp64Declare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, @@ -159,6 +182,7 @@ def template RegMiscRegOp64Constructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -168,6 +192,7 @@ class %(class_name)s : public %(base_class)s { private: bool data; + %(reg_idx_arr_decl)s; public: // Constructor @@ -180,6 +205,7 @@ def template XPauthOpRegRegConstructor {{ %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest) { + %(set_reg_idx_arr)s; data = bits(machInst, 10); %(constructor)s; } @@ -188,6 +214,9 @@ def template XPauthOpRegRegConstructor {{ def template RegNoneDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest); @@ -200,6 +229,7 @@ def template RegNoneConstructor {{ %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; diff --git a/src/arch/arm/isa/templates/mult.isa b/src/arch/arm/isa/templates/mult.isa index 79cc40fa4..f30bc794a 100644 --- a/src/arch/arm/isa/templates/mult.isa +++ b/src/arch/arm/isa/templates/mult.isa @@ -38,6 +38,9 @@ def template Mult3Declare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _reg0, @@ -52,6 +55,7 @@ def template Mult3Constructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _reg0, _reg1, _reg2) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -64,6 +68,9 @@ def template Mult3Constructor {{ def template Mult4Declare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, @@ -80,6 +87,7 @@ def template Mult4Constructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _reg0, _reg1, _reg2, _reg3) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { diff --git a/src/arch/arm/isa/templates/neon.isa b/src/arch/arm/isa/templates/neon.isa index 33e37b7b9..7e9b2b10e 100644 --- a/src/arch/arm/isa/templates/neon.isa +++ b/src/arch/arm/isa/templates/neon.isa @@ -52,6 +52,9 @@ def template NeonRegRegRegOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; @@ -62,6 +65,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -78,6 +82,9 @@ def template NeonRegRegRegImmOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; @@ -89,6 +96,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -105,6 +113,9 @@ def template NeonRegRegImmOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; @@ -115,6 +126,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -131,6 +143,9 @@ def template NeonRegImmOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; @@ -139,6 +154,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -155,6 +171,9 @@ def template NeonRegRegOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; @@ -165,6 +184,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { diff --git a/src/arch/arm/isa/templates/neon64.isa b/src/arch/arm/isa/templates/neon64.isa index ef353b933..f19f89daa 100644 --- a/src/arch/arm/isa/templates/neon64.isa +++ b/src/arch/arm/isa/templates/neon64.isa @@ -43,6 +43,9 @@ def template NeonX2RegOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; @@ -53,6 +56,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -64,6 +68,9 @@ def template NeonX2RegImmOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; @@ -75,6 +82,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -86,6 +94,9 @@ def template NeonX1RegOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; @@ -94,6 +105,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -105,6 +117,9 @@ def template NeonX1RegImmOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; @@ -115,6 +130,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -126,6 +142,9 @@ def template NeonX1Reg2ImmOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; @@ -137,6 +156,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _imm1, _imm2) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -148,6 +168,9 @@ def template NeonX1RegImmOnlyOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; @@ -156,6 +179,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -250,6 +274,9 @@ def template NeonXUnequalRegOpExecute {{ def template MicroNeonMemDeclare64 {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: // True if the base register is SP (used for SP alignment checking) bool baseIsSP; @@ -267,6 +294,7 @@ def template MicroNeonMemDeclare64 {{ _ura, _imm), baseIsSP(_baseIsSP), accSize(_accSize), eSize(_eSize) { + %(set_reg_idx_arr)s; memAccessFlags |= extraMemFlags; %(constructor)s; } @@ -431,6 +459,9 @@ def template NeonStoreCompleteAcc64 {{ def template VMemMultDeclare64 {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, RegIndex rn, RegIndex vd, @@ -442,6 +473,9 @@ def template VMemMultDeclare64 {{ def template VMemSingleDeclare64 {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, RegIndex rn, RegIndex vd, @@ -460,6 +494,7 @@ def template VMemMultConstructor64 {{ "%(mnemonic)s", machInst, %(op_class)s, rn, vd, rm, _eSize, _dataSize, _numStructElems, _numRegs, _wb) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -474,6 +509,7 @@ def template VMemSingleConstructor64 {{ _eSize, _dataSize, _numStructElems, _index, _wb, _replicate) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -481,6 +517,9 @@ def template VMemSingleConstructor64 {{ def template MicroNeonMixDeclare64 {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, uint8_t _eSize, uint8_t _dataSize, @@ -490,6 +529,7 @@ def template MicroNeonMixDeclare64 {{ _dest, _op1, _eSize, _dataSize, _numStructElems, _numRegs, _step) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -500,6 +540,9 @@ def template MicroNeonMixDeclare64 {{ def template MicroNeonMixLaneDeclare64 {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, uint8_t _eSize, uint8_t _dataSize, @@ -509,6 +552,7 @@ def template MicroNeonMixLaneDeclare64 {{ _dest, _op1, _eSize, _dataSize, _numStructElems, _lane, _step, _replicate) { + %(set_reg_idx_arr)s; %(constructor)s; } diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa index 4f06edaf6..b461aaf72 100644 --- a/src/arch/arm/isa/templates/pred.isa +++ b/src/arch/arm/isa/templates/pred.isa @@ -51,6 +51,9 @@ let {{ def template DataImmDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, @@ -66,6 +69,7 @@ def template DataImmConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _imm, _rotC) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -87,6 +91,9 @@ def template DataImmConstructor {{ def template DataRegDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, @@ -104,6 +111,7 @@ def template DataRegConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _shiftAmt, _shiftType) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -130,6 +138,9 @@ def template DataRegConstructor {{ def template DataRegRegDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, @@ -147,6 +158,7 @@ def template DataRegRegConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _shift, _shiftType) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { diff --git a/src/arch/arm/isa/templates/semihost.isa b/src/arch/arm/isa/templates/semihost.isa index da5e332a1..34fd3bd91 100644 --- a/src/arch/arm/isa/templates/semihost.isa +++ b/src/arch/arm/isa/templates/semihost.isa @@ -51,6 +51,7 @@ def template SemihostConstructor {{ %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -74,6 +75,7 @@ def template SemihostConstructor64 {{ %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; // In AArch64 there is only one instruction for issuing diff --git a/src/arch/arm/isa/templates/sve.isa b/src/arch/arm/isa/templates/sve.isa index b4b68fb74..cf77b7108 100644 --- a/src/arch/arm/isa/templates/sve.isa +++ b/src/arch/arm/isa/templates/sve.isa @@ -48,6 +48,9 @@ def template SveWideningUnaryPredOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _SElement Element; typedef _SElement SElement; @@ -62,6 +65,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _gp) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -73,6 +77,9 @@ def template SveUnaryPredOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -84,6 +91,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _gp) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -95,6 +103,9 @@ def template SveUnaryUnpredOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -104,6 +115,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -115,6 +127,9 @@ def template SveShiftAndInsertOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -125,6 +140,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, %(isSimdFp)s) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -136,6 +152,9 @@ def template SveWideImmUnpredOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -145,6 +164,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -156,6 +176,9 @@ def template SveWideImmPredOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -168,6 +191,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm, _gp, _isMerging) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -179,9 +203,13 @@ def template SveBinImmUnpredOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; + public: // Constructor %(class_name)s(ExtMachInst machInst, @@ -189,6 +217,7 @@ class %(class_name)s : public %(base_class)s : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -200,6 +229,9 @@ def template SveBinImmPredOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -211,6 +243,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm, _gp) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -222,6 +255,9 @@ def template SveBinDestrPredOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -233,6 +269,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op2, _gp) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -244,6 +281,9 @@ def template SveBinConstrPredOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -256,6 +296,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _gp, _predType) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -267,6 +308,9 @@ def template SveBinUnpredOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -278,6 +322,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -289,6 +334,9 @@ def template SveBinIdxUnpredOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -300,6 +348,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _index) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -311,6 +360,9 @@ def template SvePredLogicalOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -323,6 +375,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _gp, _isSel) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -334,6 +387,9 @@ def template SveCmpOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -345,6 +401,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _gp) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -356,6 +413,9 @@ def template SveIntCmpOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -367,6 +427,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _gp, %(op2IsWide)s) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -378,6 +439,9 @@ def template SveCmpImmOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -389,6 +453,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _imm, _gp) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -400,6 +465,9 @@ def template SveTerPredOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -411,6 +479,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _gp) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -422,6 +491,9 @@ def template SveTerImmUnpredOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -433,6 +505,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -444,6 +517,9 @@ def template SveReducOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -455,6 +531,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _gp) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -466,6 +543,9 @@ def template SveWideningReducOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _SElement Element; typedef _SElement SElement; @@ -480,6 +560,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _gp) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -491,6 +572,9 @@ def template SveIndexIIOpDeclare {{ template class SveIndexII : public SveIndexIIOp { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -502,6 +586,7 @@ class SveIndexII : public SveIndexIIOp SveIndexIIOp("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm1, _imm2) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -513,6 +598,9 @@ def template SveIndexIROpDeclare {{ template class SveIndexIR : public SveIndexIROp { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -524,6 +612,7 @@ class SveIndexIR : public SveIndexIROp SveIndexIROp("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm, _op) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -535,6 +624,9 @@ def template SveIndexRIOpDeclare {{ template class SveIndexRI : public SveIndexRIOp { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -546,6 +638,7 @@ class SveIndexRI : public SveIndexRIOp SveIndexRIOp("%(mnemonic)s", machInst, %(op_class)s, _dest, _op, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -557,6 +650,9 @@ def template SveIndexRROpDeclare {{ template class SveIndexRR : public SveIndexRROp { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -568,6 +664,7 @@ class SveIndexRR : public SveIndexRROp SveIndexRROp("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -579,6 +676,9 @@ def template SvePredCountOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -588,6 +688,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, %(srcIs32b)s, %(destIsVec)s) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -599,6 +700,9 @@ def template SvePredCountPredOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -609,6 +713,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _gp) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -621,6 +726,9 @@ def template SvePtrueOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -630,6 +738,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint8_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -641,6 +750,9 @@ def template SveAdrOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -653,6 +765,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _base, _offset, _mult, _offsetFormat) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -664,6 +777,9 @@ def template SveWhileOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -674,6 +790,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, %(srcIs32b)s) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -685,6 +802,9 @@ def template SveCompTermOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -693,6 +813,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -704,6 +825,9 @@ def template SveIntCmpImmOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -714,6 +838,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _gp) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -725,6 +850,9 @@ def template SveElemCountOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -735,6 +863,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _pattern, _imm, %(dstIsVec)s, %(dstIs32b)s) { + %(set_reg_idx_arr)s; %(constructor)s; esize = sizeof(Element); } @@ -746,12 +875,16 @@ class %(class_name)s : public %(base_class)s def template SvePartBrkOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _gp, _op1, %(isMerging)s) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -764,12 +897,16 @@ def template SvePartBrkPropOpDeclare {{ // instantiating with uint8_t class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _gp) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _gp) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -781,6 +918,9 @@ def template SveSelectOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -791,6 +931,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _gp, %(isCond)s, %(isScalar)s, %(isSimdFp)s) { + %(set_reg_idx_arr)s; %(constructor)s; scalar_width = (sizeof(Element) == 8) ? 64 : 32; } @@ -803,6 +944,9 @@ def template SveUnpackOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _SElement Element; typedef _SElement SElement; @@ -814,6 +958,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -824,10 +969,14 @@ class %(class_name)s : public %(base_class)s def template SvePredicateTestOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _gp) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _gp) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -838,10 +987,14 @@ class %(class_name)s : public %(base_class)s def template SvePredUnaryOpWImplicitSrcDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst, IntRegIndex _dest) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -852,10 +1005,14 @@ class %(class_name)s : public %(base_class)s def template SvePredUnaryPredOpWImplicitSrcDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _gp) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _gp) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -866,10 +1023,14 @@ class %(class_name)s : public %(base_class)s def template SvePredUnaryOpWImplicitDstDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -880,10 +1041,14 @@ class %(class_name)s : public %(base_class)s def template SveOpWImplicitSrcDstDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: %(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -895,6 +1060,9 @@ def template SveWideningTerImmOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _DElement Element; typedef _SElement SElement; @@ -908,6 +1076,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; esize = sizeof(Element); } @@ -920,6 +1089,9 @@ def template SveWideningTerOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _DElement Element; typedef _SElement SElement; @@ -933,6 +1105,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2) { + %(set_reg_idx_arr)s; %(constructor)s; esize = sizeof(Element); } @@ -945,6 +1118,9 @@ def template SveComplexOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -957,6 +1133,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _gp, _rot) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -968,6 +1145,9 @@ def template SveComplexIndexOpDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -980,6 +1160,7 @@ class %(class_name)s : public %(base_class)s %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _rot, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } diff --git a/src/arch/arm/isa/templates/sve_mem.isa b/src/arch/arm/isa/templates/sve_mem.isa index 829f025c4..8bfb423e3 100644 --- a/src/arch/arm/isa/templates/sve_mem.isa +++ b/src/arch/arm/isa/templates/sve_mem.isa @@ -36,6 +36,9 @@ def template SveMemFillSpillOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef uint8_t TPElem; typedef uint8_t RegElemType; @@ -47,6 +50,7 @@ def template SveMemFillSpillOpDeclare {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _base, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -67,6 +71,9 @@ def template SveContigMemSSOpDeclare {{ %(tpl_header)s class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef RegElemType TPElem; @@ -77,6 +84,7 @@ def template SveContigMemSSOpDeclare {{ %(base_class)s(mnem, machInst, %(op_class)s, _dest, _gp, _base, _offset) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -97,6 +105,9 @@ def template SveContigMemSIOpDeclare {{ %(tpl_header)s class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef RegElemType TPElem; @@ -107,6 +118,7 @@ def template SveContigMemSIOpDeclare {{ %(base_class)s(mnem, machInst, %(op_class)s, _dest, _gp, _base, _imm) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -400,6 +412,9 @@ def template SveIndexedMemVIMicroopDeclare {{ %(tpl_header)s class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef RegElemType TPElem; @@ -425,6 +440,7 @@ def template SveIndexedMemVIMicroopDeclare {{ firstFault(_firstFault), memAccessFlags(ArmISA::TLB::AllowUnaligned) { + %(set_reg_idx_arr)s; %(constructor)s; if (_opClass == MemReadOp && elemIndex == 0) { // The first micro-op is responsible for pinning the @@ -478,6 +494,9 @@ def template SveIndexedMemSVMicroopDeclare {{ %(tpl_header)s class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef RegElemType TPElem; @@ -509,6 +528,7 @@ def template SveIndexedMemSVMicroopDeclare {{ numElems(_numElems), firstFault(_firstFault), memAccessFlags(ArmISA::TLB::AllowUnaligned) { + %(set_reg_idx_arr)s; %(constructor)s; if (_opClass == MemReadOp && elemIndex == 0) { // The first micro-op is responsible for pinning the @@ -755,11 +775,14 @@ def template SveFirstFaultWritebackMicroopDeclare {{ StaticInst *macroOp; public: + %(reg_idx_arr_decl)s; + SveFirstFaultWritebackMicroop(const char* mnem, ExtMachInst machInst, OpClass __opClass, int _numElems, StaticInst *_macroOp) : MicroOp(mnem, machInst, __opClass), numElems(_numElems), macroOp(_macroOp) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -807,6 +830,9 @@ def template SveFirstFaultWritebackMicroopExecute {{ def template SveGatherLoadCpySrcVecMicroopDeclare {{ class SveGatherLoadCpySrcVecMicroop : public MicroOp { + private: + %(reg_idx_arr_decl)s; + protected: IntRegIndex op1; @@ -817,6 +843,7 @@ def template SveGatherLoadCpySrcVecMicroopDeclare {{ IntRegIndex _op1, StaticInst *_macroOp) : MicroOp(mnem, machInst, SimdAluOp), op1(_op1), macroOp(_macroOp) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -856,6 +883,9 @@ def template SveStructMemSIMicroopDeclare {{ template class %(class_name)s : public %(base_class)s { + public: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -1129,6 +1159,9 @@ def template SveStructMemSSMicroopDeclare {{ template class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -1154,6 +1187,7 @@ def template SveStructMemSSMicroopDeclare {{ numRegs(_numRegs), regIndex(_regIndex), memAccessFlags(ArmISA::TLB::AllowUnaligned) { + %(set_reg_idx_arr)s; %(constructor)s; baseIsSP = isSP(_base); } @@ -1212,6 +1246,9 @@ def template SveIntrlvMicroopDeclare {{ template class %(class_name)s: public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -1229,6 +1266,7 @@ def template SveIntrlvMicroopDeclare {{ MicroOp(mnem, machInst, SimdAluOp), dest(_dest), op1(_op1), numRegs(_numRegs), regIndex(_regIndex), macroOp(_macroOp) { + %(set_reg_idx_arr)s; %(constructor)s; } @@ -1250,6 +1288,9 @@ def template SveDeIntrlvMicroopDeclare {{ template class %(class_name)s : public %(base_class)s { + public: + %(reg_idx_arr_decl)s; + protected: typedef _Element Element; typedef _Element TPElem; @@ -1266,6 +1307,7 @@ def template SveDeIntrlvMicroopDeclare {{ MicroOp(mnem, machInst, SimdAluOp), dest(_dest), numRegs(_numRegs), regIndex(_regIndex), macroOp(_macroOp) { + %(set_reg_idx_arr)s; %(constructor)s; } diff --git a/src/arch/arm/isa/templates/vfp.isa b/src/arch/arm/isa/templates/vfp.isa index 5481350cb..26303cb24 100644 --- a/src/arch/arm/isa/templates/vfp.isa +++ b/src/arch/arm/isa/templates/vfp.isa @@ -98,6 +98,9 @@ let {{ def template FpRegRegOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, @@ -114,6 +117,7 @@ def template FpRegRegOpConstructor {{ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, mode) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -126,6 +130,9 @@ def template FpRegRegOpConstructor {{ def template FpRegImmOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, @@ -140,6 +147,7 @@ def template FpRegImmOpConstructor {{ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm, mode) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -152,6 +160,9 @@ def template FpRegImmOpConstructor {{ def template FpRegRegImmOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, @@ -170,6 +181,7 @@ def template FpRegRegImmOpConstructor {{ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _imm, mode) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -182,6 +194,9 @@ def template FpRegRegImmOpConstructor {{ def template FpRegRegRegOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, @@ -200,6 +215,7 @@ def template FpRegRegRegOpConstructor {{ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, mode) { + %(set_reg_idx_arr)s; %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { for (int x = 0; x < _numDestRegs; x++) { @@ -212,6 +228,9 @@ def template FpRegRegRegOpConstructor {{ def template FpRegRegRegCondOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, @@ -232,6 +251,7 @@ def template FpRegRegRegCondOpConstructor {{ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _cond, mode) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; diff --git a/src/arch/arm/isa/templates/vfp64.isa b/src/arch/arm/isa/templates/vfp64.isa index 4ffb42ff0..2548940bb 100644 --- a/src/arch/arm/isa/templates/vfp64.isa +++ b/src/arch/arm/isa/templates/vfp64.isa @@ -42,6 +42,7 @@ def template AA64FpRegRegOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, mode) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -52,6 +53,7 @@ def template AA64FpRegImmOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm, mode) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -63,6 +65,7 @@ def template AA64FpRegRegImmOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _imm, mode) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -74,6 +77,7 @@ def template AA64FpRegRegRegOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, mode) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; @@ -81,6 +85,9 @@ def template AA64FpRegRegRegOpConstructor {{ def template AA64FpRegRegRegRegOpDeclare {{ class %(class_name)s : public %(base_class)s { + private: + %(reg_idx_arr_decl)s; + public: // Constructor %(class_name)s(ExtMachInst machInst, @@ -97,6 +104,7 @@ def template AA64FpRegRegRegRegOpConstructor {{ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1, _op2, _op3, mode) { + %(set_reg_idx_arr)s; %(constructor)s; } }}; -- 2.30.2