From d1663ccb4c664b0f544ed5d6f0761f3ae2435199 Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Wed, 17 Jun 2015 15:50:11 -0700 Subject: [PATCH] i965/bxt: Add basic Broxton infrastructure The thread counts and URB information are all speculative numbers that were based on some CHV numbers at the time. v2: Originally this patch had PCI IDs. I've moved that to a new patch at the end of the series. Remove is_cherryview hack. Add PCI ids. These match the ones defined in the kernel. The only one tested by us is 0x0a84. Capitalize the hex string (Mark) Signed-off-by: Ben Widawsky Tested-by: "Lecluse, Philippe" Reviewed-by: Mark Janes --- include/pci_ids/i965_pci_ids.h | 3 +++ src/mesa/drivers/dri/i965/brw_context.c | 1 + src/mesa/drivers/dri/i965/brw_context.h | 1 + src/mesa/drivers/dri/i965/brw_device_info.c | 16 ++++++++++++++++ src/mesa/drivers/dri/i965/brw_device_info.h | 1 + 5 files changed, 22 insertions(+) diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index 8d757aaa767..8a425999429 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -128,3 +128,6 @@ CHIPSET(0x22B0, chv, "Intel(R) HD Graphics (Cherryview)") CHIPSET(0x22B1, chv, "Intel(R) HD Graphics (Cherryview)") CHIPSET(0x22B2, chv, "Intel(R) HD Graphics (Cherryview)") CHIPSET(0x22B3, chv, "Intel(R) HD Graphics (Cherryview)") +CHIPSET(0x0A84, bxt, "Intel(R) HD Graphics (Broxton)") +CHIPSET(0x1A84, bxt, "Intel(R) HD Graphics (Broxton)") +CHIPSET(0x5A84, bxt, "Intel(R) HD Graphics (Broxton)") diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index cf408830620..4b51fe5da56 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -715,6 +715,7 @@ brwCreateContext(gl_api api, brw->is_baytrail = devinfo->is_baytrail; brw->is_haswell = devinfo->is_haswell; brw->is_cherryview = devinfo->is_cherryview; + brw->is_broxton = devinfo->is_broxton; brw->has_llc = devinfo->has_llc; brw->has_hiz = devinfo->has_hiz_and_separate_stencil; brw->has_separate_stencil = devinfo->has_hiz_and_separate_stencil; diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 85d8f14a006..3553f6ec48c 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1117,6 +1117,7 @@ struct brw_context bool is_baytrail; bool is_haswell; bool is_cherryview; + bool is_broxton; bool has_hiz; bool has_separate_stencil; diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c b/src/mesa/drivers/dri/i965/brw_device_info.c index 97243a47293..342e56622b7 100644 --- a/src/mesa/drivers/dri/i965/brw_device_info.c +++ b/src/mesa/drivers/dri/i965/brw_device_info.c @@ -334,6 +334,22 @@ static const struct brw_device_info brw_device_info_skl_gt3 = { .supports_simd16_3src = true, }; +static const struct brw_device_info brw_device_info_bxt = { + GEN9_FEATURES, + .is_broxton = 1, + .gt = 1, + .has_llc = false, + .max_vs_threads = 112, + .max_gs_threads = 112, + .max_wm_threads = 32, + .urb = { + .size = 64, + .min_vs_entries = 34, + .max_vs_entries = 640, + .max_gs_entries = 256, + } +}; + const struct brw_device_info * brw_get_device_info(int devid, int revision) { diff --git a/src/mesa/drivers/dri/i965/brw_device_info.h b/src/mesa/drivers/dri/i965/brw_device_info.h index 65c024ceeed..7b7a1fc046a 100644 --- a/src/mesa/drivers/dri/i965/brw_device_info.h +++ b/src/mesa/drivers/dri/i965/brw_device_info.h @@ -35,6 +35,7 @@ struct brw_device_info bool is_baytrail; bool is_haswell; bool is_cherryview; + bool is_broxton; bool has_hiz_and_separate_stencil; bool must_use_separate_stencil; -- 2.30.2