From d17e77f1f6075583d5b973030d2b68557d50f1b5 Mon Sep 17 00:00:00 2001 From: Riken Gohil Date: Tue, 1 Aug 2017 11:08:16 +0100 Subject: [PATCH] cpu-tester: Added ExitGen to TrafficGen Added the ExitGen to the TrafficGenerator which allows an EXIT state to be added to the TrafficGen configuration file. Entering this state will cause the simulation to exit immediately. Please note that if multiple TrafficGen instances have an EXIT state, the first of these to be encountered will cause the simulation to terminate. Change-Id: Ieea51f05ffb780771f007787a2b119f79143d0c1 Reviewed-by: Sascha Bischoff Reviewed-on: https://gem5-review.googlesource.com/5723 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/cpu/testers/traffic_gen/SConscript | 1 + src/cpu/testers/traffic_gen/exit_gen.cc | 66 ++++++++++++++++++++ src/cpu/testers/traffic_gen/exit_gen.hh | 71 ++++++++++++++++++++++ src/cpu/testers/traffic_gen/traffic_gen.cc | 5 +- src/cpu/testers/traffic_gen/traffic_gen.hh | 1 + 5 files changed, 143 insertions(+), 1 deletion(-) create mode 100644 src/cpu/testers/traffic_gen/exit_gen.cc create mode 100644 src/cpu/testers/traffic_gen/exit_gen.hh diff --git a/src/cpu/testers/traffic_gen/SConscript b/src/cpu/testers/traffic_gen/SConscript index d73819b0c..74d027970 100644 --- a/src/cpu/testers/traffic_gen/SConscript +++ b/src/cpu/testers/traffic_gen/SConscript @@ -47,6 +47,7 @@ if env['HAVE_PROTOBUF']: Source('base_gen.cc') Source('dram_gen.cc') Source('dram_rot_gen.cc') + Source('exit_gen.cc') Source('idle_gen.cc') Source('linear_gen.cc') Source('random_gen.cc') diff --git a/src/cpu/testers/traffic_gen/exit_gen.cc b/src/cpu/testers/traffic_gen/exit_gen.cc new file mode 100644 index 000000000..8a07160bb --- /dev/null +++ b/src/cpu/testers/traffic_gen/exit_gen.cc @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2017 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Riken Gohil + */ + +#include "base/misc.hh" +#include "base/trace.hh" +#include "debug/TrafficGen.hh" +#include "exit_gen.hh" +#include "sim/sim_exit.hh" + +void +ExitGen::enter() +{ + DPRINTF(TrafficGen, "%s has encountered the exit state and will " + "terminate the simulation.\n", name()); + exitSimLoop(name() + " has encountered the exit state and will " + "terminate the simulation.\n"); +} + +PacketPtr +ExitGen::getNextPacket() +{ + panic("Simulation should have exited"); + return NULL; +} + +Tick +ExitGen::nextPacketTick(bool elastic, Tick delay) const +{ + return MaxTick; +} diff --git a/src/cpu/testers/traffic_gen/exit_gen.hh b/src/cpu/testers/traffic_gen/exit_gen.hh new file mode 100644 index 000000000..45087e661 --- /dev/null +++ b/src/cpu/testers/traffic_gen/exit_gen.hh @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2017 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Riken Gohil + */ + +/** + * @file + * Declaration of the exit generator that ends the simulation + */ + +#ifndef __CPU_TRAFFIC_GEN_EXIT_GEN_HH__ +#define __CPU_TRAFFIC_GEN_EXIT_GEN_HH__ + +#include "base_gen.hh" + +/** + * The exit generator exits from the simulation + * once entered. + */ +class ExitGen : public BaseGen +{ + + public: + + ExitGen(const std::string& _name, MasterID master_id, Tick _duration) + : BaseGen(_name, master_id, _duration) + { } + + void enter(); + + PacketPtr getNextPacket(); + + Tick nextPacketTick(bool elastic, Tick delay) const; + +}; + +#endif diff --git a/src/cpu/testers/traffic_gen/traffic_gen.cc b/src/cpu/testers/traffic_gen/traffic_gen.cc index 9d8732902..7668c5141 100644 --- a/src/cpu/testers/traffic_gen/traffic_gen.cc +++ b/src/cpu/testers/traffic_gen/traffic_gen.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2013, 2016 ARM Limited + * Copyright (c) 2012-2013, 2016-2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -305,6 +305,9 @@ TrafficGen::parseConfig() } else if (mode == "IDLE") { states[id] = new IdleGen(name(), masterID, duration); DPRINTF(TrafficGen, "State: %d IdleGen\n", id); + } else if (mode == "EXIT") { + states[id] = new ExitGen(name(), masterID, duration); + DPRINTF(TrafficGen, "State: %d ExitGen\n", id); } else if (mode == "LINEAR" || mode == "RANDOM" || mode == "DRAM" || mode == "DRAM_ROTATE") { uint32_t read_percent; diff --git a/src/cpu/testers/traffic_gen/traffic_gen.hh b/src/cpu/testers/traffic_gen/traffic_gen.hh index e78b82e95..6c2c16382 100644 --- a/src/cpu/testers/traffic_gen/traffic_gen.hh +++ b/src/cpu/testers/traffic_gen/traffic_gen.hh @@ -48,6 +48,7 @@ #include "cpu/testers/traffic_gen/base_gen.hh" #include "cpu/testers/traffic_gen/dram_gen.hh" #include "cpu/testers/traffic_gen/dram_rot_gen.hh" +#include "cpu/testers/traffic_gen/exit_gen.hh" #include "cpu/testers/traffic_gen/idle_gen.hh" #include "cpu/testers/traffic_gen/linear_gen.hh" #include "cpu/testers/traffic_gen/random_gen.hh" -- 2.30.2