From d198c8b6c7fd057022e3e44a6afd9c93efe65e54 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 26 Oct 2018 04:27:32 +0100 Subject: [PATCH] add max elwidth resolver on add operation result now respects the element width of the 2 source operands --- riscv/sv.cc | 14 +++++--------- riscv/sv_insn_redirect.cc | 3 ++- riscv/sv_reg.h | 2 +- 3 files changed, 8 insertions(+), 11 deletions(-) diff --git a/riscv/sv.cc b/riscv/sv.cc index 0012649..5cfc4c0 100644 --- a/riscv/sv.cc +++ b/riscv/sv.cc @@ -12,17 +12,13 @@ int get_bitwidth(uint8_t elwidth, int xlen) } } -/* -int to_elwidth(uint8_t bitwidth, int xlen) +uint8_t maxelwidth(uint8_t wid1, uint8_t wid2) { - switch (bitwidth) { - case xlen: return 0; - case 8: return 1; - case 16: return 2; - default: return 3; - } + if (wid1 == 0 || wid2 == 0) { + return 0; + } + return std::max(wid1, wid2); } -*/ sv_insn_t::sv_insn_t(processor_t *pr, bool _sv_enabled, insn_bits_t bits, unsigned int f, int _xlen, diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index 3c9fa05..3417e69 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -363,7 +363,8 @@ sv_reg_t sv_proc_t::rv_add(sv_reg_t const & lhs, sv_reg_t const & rhs) } else { // nope: zero-extend. result = zext_bwid(result, bitwidth); } - return sv_reg_t(result, xlen); // XXX TODO: bitwidth + uint8_t reswidth = maxelwidth(lhs.get_elwidth(), rhs.get_elwidth()); + return sv_reg_t(result, xlen, reswidth); // XXX TODO: bitwidth } sv_reg_t sv_proc_t::rv_sub(sv_reg_t const & lhs, sv_reg_t const & rhs) diff --git a/riscv/sv_reg.h b/riscv/sv_reg.h index 6908189..5dfcb35 100644 --- a/riscv/sv_reg.h +++ b/riscv/sv_reg.h @@ -7,7 +7,7 @@ #define zext_bwid(x,wid) (((reg_t)(x) << (64-wid)) >> (64-wid)) extern int get_bitwidth(uint8_t elwidth, int xlen); -//extern int to_elwidth(uint8_t bitwidth, int xlen); +extern uint8_t maxelwidth(uint8_t bwid1, uint8_t bwid2); class sv_sreg_t; -- 2.30.2