From d1a81ee01e1ae4c0579b002bfa96dd5623e67dc4 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 1 Jun 2022 15:31:06 +0100 Subject: [PATCH] --- openpower/sv/svp64_quirks.mdwn | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index 2543897ca..2b43e255c 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -52,10 +52,27 @@ makes no sense at all, such as `sc` or `mtmsr`). The categories are: * Condition Register Field operations * branch +Arithmetic (known as "normal" mode) is where Scalar and Parallel +Reduction can be done: Saturation as well, and two new innovative +modes for Vector ISAs: data-dependent fail-first and predicate result. +Reduction and Saturation are common to see in Vector ISAs: it is just +that they are usually added as explicit instructions. In SVP64 these +concepts are applied in the abstract general form, which takes some +getting used to, as it may result in invalid results, but ultimately +it is critical to think in terms of the "rules", that everything is +Scalar instructions in strict Program Order. + Branch is the one and only place where the Scalar (non-prefixed) operations differ from the Vector (element) instructions, as explained in a separate section. - +The +RM bits can be used for other purposes because the Arithmetic modes +make no sense at all for a Branch. +Almost the entire +SVP64 RM Field is interpreted differently from other Modes, in +order to support a wide range of parallel boolean condition options +which are expected of a Vector / GPU ISA. These save a considerable +number of instructions in tight inner loop situations. # CR weird instructions -- 2.30.2