From d1baae36a69b6e99a09e9c76eae863927616008e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 12 Nov 2018 09:43:31 +0100 Subject: [PATCH] platforms/versa_ecp5: add ecp5 soc hat ios --- litex/boards/platforms/versa_ecp5.py | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/litex/boards/platforms/versa_ecp5.py b/litex/boards/platforms/versa_ecp5.py index 8ecb2633..00b77931 100644 --- a/litex/boards/platforms/versa_ecp5.py +++ b/litex/boards/platforms/versa_ecp5.py @@ -33,7 +33,6 @@ _io = [ Subsignal("tx", Pins("A11"), IOStandard("LVCMOS33")), ), - ("eth_clocks", 0, Subsignal("tx", Pins("P19")), Subsignal("rx", Pins("L20")), @@ -68,6 +67,27 @@ _io = [ ] +_ecp5_soc_hat_io = [ + ("sdram_clock", 0, Pins("E14"), IOStandard("LVCMOS33")), + ("sdram", 0, + Subsignal("a", Pins( + "C6 E15 A16 B16 D15 C15 B15 E12", + "D12 B10 C7 A9 C10")), + Subsignal("dq", Pins( + "B19 B12 B9 E6 D6 E7 D7 B11", + "C14 A14 E13 D13 C13 B13 A13 A12")), + Subsignal("we_n", Pins("E9")), + Subsignal("ras_n", Pins("B8")), + Subsignal("cas_n", Pins("D9")), + Subsignal("cs_n", Pins("C8")), + Subsignal("cke", Pins("D11")), + Subsignal("ba", Pins("D8 E8")), + Subsignal("dm", Pins("B6 D14")), + IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST") + ), +] + + class Platform(LatticePlatform): default_clk_name = "clk100" default_clk_period = 10 -- 2.30.2