From d1cd24a457fe7d935558975bc1d401e42bbd177e Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 10 Jun 2022 15:00:07 +0200
Subject: [PATCH] Update manual

---
 manual/command-reference-manual.tex | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index 4108527d8..edc8af6e6 100644
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -7838,6 +7838,11 @@ Add Verilog library directories. Verific will search in this directories to
 find undefined modules.
 
 
+    verific -vlog-libext <extension>..
+
+Add Verilog library extensions, used when searching in library directories.
+
+
     verific -vlog-define <macro>[=<value>]..
 
 Add Verilog defines.
@@ -8057,6 +8062,9 @@ Options:
         Do not change the width of memory address ports. Use this options in
         flows that use the 'memory_memx' pass.
 
+    -mux_undef
+        remove 'undef' inputs from $mux, $pmux and $_MUX_ cells
+
     -keepdc
         Do not optimize explicit don't-care values.
 \end{lstlisting}
-- 
2.30.2