From d1df8e61d9b2da83557bdc5f92838a9b625e30db Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 8 Dec 2021 16:42:32 +0000 Subject: [PATCH] remove MSR and add CIA to MMU Input Record --- src/soc/fu/mmu/mmu_input_record.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/fu/mmu/mmu_input_record.py b/src/soc/fu/mmu/mmu_input_record.py index 109d2d38..281e8dd8 100644 --- a/src/soc/fu/mmu/mmu_input_record.py +++ b/src/soc/fu/mmu/mmu_input_record.py @@ -13,7 +13,7 @@ class CompMMUOpSubset(CompOpSubsetBase): layout = (('insn_type', MicrOp), ('fn_unit', Function), ('insn', 32), - ('msr', 64), # TODO: a lot less bits. only need PR, DR, SF + ('cia', 64), # for instruction fault (MMU PTE lookup) ('zero_a', 1), ) super().__init__(layout, name=name) -- 2.30.2