From d1f65e5e99cf4e8384dce2dd1602248fd459e15b Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 24 Nov 2017 00:19:56 +0100 Subject: [PATCH] radeonsi: clear PIPE_IMAGE_ACCESS_WRITE when it's invalid to be on the safe side MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Tested-by: Dieter Nützel Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_descriptors.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 69371ea8910..5fbca541952 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -688,6 +688,16 @@ static void si_set_shader_image_desc(struct si_context *ctx, unsigned level = view->u.tex.level; unsigned width, height, depth, hw_level; bool uses_dcc = vi_dcc_enabled(tex, level); + unsigned access = view->access; + + /* Clear the write flag when writes can't occur. + * Note that DCC_DECOMPRESS for MSAA doesn't work in some cases, + * so we don't wanna trigger it. + */ + if (tex->is_depth || tex->resource.b.b.nr_samples >= 2) { + assert(!"Z/S and MSAA image stores are not supported"); + access &= ~PIPE_IMAGE_ACCESS_WRITE; + } assert(!tex->is_depth); assert(tex->fmask.size == 0); -- 2.30.2