From d200b30b1f6b0baf3753adfaeaad6d3f40bac58a Mon Sep 17 00:00:00 2001
From: bugzilla-daemon <bugzilla-daemon@libre-soc.org>
Date: Sat, 6 Jun 2020 20:33:53 +0000
Subject: [PATCH] [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise
 that RA (src1) can be zero

---
 18/b1eb921c361044c9fb600a030b957bbe26f2a2 | 92 +++++++++++++++++++++++
 1 file changed, 92 insertions(+)
 create mode 100644 18/b1eb921c361044c9fb600a030b957bbe26f2a2

diff --git a/18/b1eb921c361044c9fb600a030b957bbe26f2a2 b/18/b1eb921c361044c9fb600a030b957bbe26f2a2
new file mode 100644
index 0000000..35ec37a
--- /dev/null
+++ b/18/b1eb921c361044c9fb600a030b957bbe26f2a2
@@ -0,0 +1,92 @@
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+From: bugzilla-daemon@libre-soc.org
+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Sat, 06 Jun 2020 20:33:53 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: cestrauss@gmail.com
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution: 
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: cestrauss@gmail.com
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+Message-ID: <bug-336-13-rdgkKa0ZXL@https.bugs.libre-soc.org/>
+In-Reply-To: <bug-336-13@https.bugs.libre-soc.org/>
+References: <bug-336-13@https.bugs.libre-soc.org/>
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+Auto-Submitted: auto-generated
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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-- 
2.30.2