From d206eca03b8aa7bb982fb2486c02c90a61354066 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 2 Jul 2019 11:36:26 +0200 Subject: [PATCH] Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53 Signed-off-by: Clifford Wolf --- frontends/verilog/verilog_lexer.l | 2 ++ 1 file changed, 2 insertions(+) diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index d3fd91473..951d9c66f 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -193,6 +193,8 @@ YOSYS_NAMESPACE_END to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some global state.. its a mess) */ [a-zA-Z_$][a-zA-Z0-9_$]*/[ \t\r\n]*:[ \t\r\n]*(assert|assume|cover|restrict)[^a-zA-Z0-9_$\.] { + if (!strcmp(yytext, "default")) + return TOK_DEFAULT; frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); return TOK_SVA_LABEL; } -- 2.30.2