From d20b197326aabbe769dac42793721ba1c0c4e750 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 1 Mar 2022 15:22:20 +0000 Subject: [PATCH] fix up simulation to be more like VERSA_ECP5 * use MT4164M16 instead of MT41256M16 * add a Chip-Select line (dram_cs_n) which is currently inverted * reduce the number of address lines in the simulated platform --- gram/simulation/icarusecpix5platform.py | 8 +++++--- gram/simulation/simsoc.py | 7 ++++--- gram/simulation/simsoctb.v | 11 ++++++++++- 3 files changed, 19 insertions(+), 7 deletions(-) diff --git a/gram/simulation/icarusecpix5platform.py b/gram/simulation/icarusecpix5platform.py index e3520c0..b3b5a1b 100644 --- a/gram/simulation/icarusecpix5platform.py +++ b/gram/simulation/icarusecpix5platform.py @@ -28,13 +28,15 @@ class IcarusECPIX5Platform(LatticeECP5Platform): Resource("ddr3", 0, Subsignal("rst", Pins("fake", dir="o")), # for sim - Subsignal("clk", Pins("H3", dir="o")), - #Subsignal("clk", DiffPairs("H3", "J3", dir="o"), Attrs(IO_TYPE="SSTL135D_I")), + #Subsignal("clk", Pins("H3", dir="o")), + Subsignal("clk", DiffPairs("H3", "J3", dir="o"), Attrs(IO_TYPE="SSTL135D_I")), Subsignal("clk_en", Pins("P1", dir="o")), Subsignal("we", PinsN("R3", dir="o")), + Subsignal("cs", PinsN("fake2", dir="o")), # for sim Subsignal("ras", PinsN("T3", dir="o")), Subsignal("cas", PinsN("P2", dir="o")), - Subsignal("a", Pins("T5 M3 L3 V6 K2 W6 K3 L1 H2 L2 N1 J1 M1 K1", dir="o")), + #Subsignal("a", Pins("T5 M3 L3 V6 K2 W6 K3 L1 H2 L2 N1 J1 M1 K1", dir="o")), + Subsignal("a", Pins("T5 M3 L3 V6 K2 W6 K3 L1 H2 L2 N1 J1 M1", dir="o")), Subsignal("ba", Pins("U6 N3 N4", dir="o")), Subsignal("dqs", DiffPairs("V4 V1", "U5 U2", dir="io"), Attrs(IO_TYPE="SSTL135D_I")), Subsignal("dq", Pins("T4 W4 R4 W5 R6 P6 P5 P4 R1 W3 T2 V3 U3 W1 T1 W2", dir="io")), diff --git a/gram/simulation/simsoc.py b/gram/simulation/simsoc.py index ba3c839..29aa35b 100644 --- a/gram/simulation/simsoc.py +++ b/gram/simulation/simsoc.py @@ -9,7 +9,7 @@ from lambdasoc.soc.base import SoC from gram.core import gramCore from gram.phy.ecp5ddrphy import ECP5DDRPHY -from gram.modules import MT41K256M16 +from gram.modules import (MT41K256M16, MT41K64M16) from gram.frontend.wishbone import gramWishbone from icarusecpix5platform import IcarusECPIX5Platform @@ -26,11 +26,12 @@ class DDR3SoC(SoC, Elaboratable): ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"}, xdr={"rst": 4, "clk":4, "a":4, "ba":4, "clk_en":4, "we_n":4, - "odt":4, "ras":4, "cas":4, "we":4}) + "cs": 4, "odt":4, "ras":4, "cas":4, "we":4}) self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins)) self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr) - ddrmodule = MT41K256M16(clk_freq, "1:2") + #ddrmodule = MT41K256M16(clk_freq, "1:2") + ddrmodule = MT41K64M16(clk_freq, "1:2") self.dramcore = DomainRenamer("dramsync")(gramCore( phy=self.ddrphy, diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v index 3ef4ad9..54c76e4 100644 --- a/gram/simulation/simsoctb.v +++ b/gram/simulation/simsoctb.v @@ -30,6 +30,7 @@ module simsoctb; wire dram_ck; wire dram_cke; wire dram_we_n; + wire dram_cs_n; wire dram_ras_n; wire dram_cas_n; wire [15:0] dram_dq; @@ -49,7 +50,7 @@ module simsoctb; .ck(dram_ck), .ck_n(~dram_ck), .cke(dram_cke), - .cs_n(1'b0), + .cs_n(~dram_cs_n), .ras_n(dram_ras_n), .cas_n(dram_cas_n), .we_n(dram_we_n), @@ -84,6 +85,7 @@ module simsoctb; .ddr3_0__clk__io(dram_ck), .ddr3_0__clk_en__io(dram_cke), .ddr3_0__we__io(dram_we_n), + .ddr3_0__cs__io(dram_cs_n), .ddr3_0__ras__io(dram_ras_n), .ddr3_0__cas__io(dram_cas_n), .ddr3_0__a__io(dram_a), @@ -111,6 +113,7 @@ module simsoctb; $dumpvars(0, dram_dqs); $dumpvars(0, dram_ck); $dumpvars(0, dram_cke); + $dumpvars(0, dram_cs_n); $dumpvars(0, dram_we_n); $dumpvars(0, dram_ras_n); $dumpvars(0, dram_cas_n); @@ -194,6 +197,12 @@ module simsoctb; wishbone_write(32'h00009000 >> 2, 8'h01); // DFII_CONTROL_SEL #2000; + // reset burst detect + //wishbone_write(32'h00008000 >> 2, 0); // burst detect reset + + // read on burst detect + //wishbone_read(32'h00008000 >> 2, tmp); // burst detect + // Read test on provisioned data, row 0, col 0-7 wishbone_read(32'h10000000 >> 2, tmp); assert_equal_32(tmp, 32'hFACECA8C); -- 2.30.2