From d20b1c029aa4e268859399c821e3f18e59efe92b Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 15 Jun 2022 00:52:58 +0100 Subject: [PATCH] --- openpower/sv/svp64_quirks.mdwn | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index 34920fdb4..85ffc48cb 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -224,6 +224,22 @@ for the type of operation (Branch, CRs, Memory, Arithmetic), and each Category has its own relevant but ultimately rational quirks. +# Abstraction between Prefix and Suffix + +In the introduction paragraph, a great fuss was made emphasising that +the Prefix is kept separate from the Suffix. The whole idea there is +that a Multi-issue Decoder and subsequent pipelines would in no way have +"back-propagation" of state that can only be determined far too late. +This *has* been preserved, however there is a hiccup. + +Examining the Power ISA 3.1 a 64-bit Prefix was introduced, EXT001. +The encoding of the prefix has 6 bits that are dedicated to letting +the hardware know what the remainder of the Prefix bits mean: how they +are formatted, even without having to examine the Suffix to which +they are applied. + +SVP64 has such pressure on its 24 + # Single Predication So named because there is a Twin Predication concept as well, Single -- 2.30.2