From d20be46eb4ffb94a9e7b2916dbc59a3666f21877 Mon Sep 17 00:00:00 2001
From: Tim Newsome <tim@sifive.com>
Date: Fri, 22 Apr 2016 15:10:23 -0700
Subject: [PATCH] When gdb connects, jump to Debug ROM and segfault.

---
 riscv/decode.h     |  7 ++++++-
 riscv/execute.cc   |  4 ++++
 riscv/gdbserver.cc |  2 +-
 riscv/processor.cc |  5 +++++
 riscv/processor.h  | 10 +---------
 5 files changed, 17 insertions(+), 11 deletions(-)

diff --git a/riscv/decode.h b/riscv/decode.h
index 784c717..d1254ee 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -229,9 +229,14 @@ private:
  * automatically generated. */
 /* TODO */
 #include "/media/sf_tnewsome/Synced/SiFive/debug-spec/core_registers.tex.h"
+#define DCSR_CAUSE_NONE         0
 #define DCSR_CAUSE_SWBP         1
+#define DCSR_CAUSE_HWBP         2
+#define DCSR_CAUSE_DEBUGINT     3
+#define DCSR_CAUSE_STEPPED      4
 #define DCSR_CAUSE_HALT         5
 
-#define DEBUG_ROM_ENTRY         0x800
+#define DEBUG_RAM               0xfffffc00       // TODO: 0x400
+#define DEBUG_ROM_ENTRY         0xfffff800       // TODO: 0x800
 
 #endif
diff --git a/riscv/execute.cc b/riscv/execute.cc
index 8b8c902..1796c38 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -53,6 +53,10 @@ static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
 // fetch/decode/execute loop
 void processor_t::step(size_t n)
 {
+  if (state.dcsr.debugint && state.dcsr.cause == DCSR_CAUSE_NONE) {
+    enter_debug_mode(DCSR_CAUSE_DEBUGINT);
+  }
+
   while (n > 0) {
     size_t instret = 0;
     reg_t pc = state.pc;
diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc
index 0fe5365..1d5c9ce 100644
--- a/riscv/gdbserver.cc
+++ b/riscv/gdbserver.cc
@@ -141,7 +141,7 @@ void gdbserver_t::accept()
 
     // gdb wants the core to be halted when it attaches.
     processor_t *p = sim->get_core(0);
-    // TODO p->set_halted(true, HR_ATTACHED);
+    p->set_debug_int();
   }
 }
 
diff --git a/riscv/processor.cc b/riscv/processor.cc
index df9a724..4ef8e02 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -119,6 +119,11 @@ void state_t::reset()
   load_reservation = -1;
 }
 
+void processor_t::set_debug_int()
+{
+  state.dcsr.debugint = true;
+}
+
 void processor_t::set_debug(bool value)
 {
   debug = value;
diff --git a/riscv/processor.h b/riscv/processor.h
index 8ac8507..1eabee4 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -90,15 +90,6 @@ struct state_t
 #endif
 };
 
-typedef enum {
-      HR_NONE,
-      HR_STEPPED,       // A single step was completed
-      HR_SWBP,          // sbreak was executed
-      HR_INTERRUPT,     // Execution interrupted by debugger
-      HR_CMDLINE,       // Command line requested that the processor start halted
-      HR_ATTACHED       // Halted because a debugger attached
-} halt_reason_t;
-
 // this class represents one processor in a RISC-V machine.
 class processor_t : public abstract_device_t
 {
@@ -106,6 +97,7 @@ public:
   processor_t(const char* isa, sim_t* sim, uint32_t id);
   ~processor_t();
 
+  void set_debug_int();
   void set_debug(bool value);
   void set_histogram(bool value);
   void reset(bool value);
-- 
2.30.2