From d20e983a625cb05c8795f73a2d47e220615cb3bb Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Wed, 3 Nov 2021 18:34:57 +0100 Subject: [PATCH] loadstore.py: add Display statement on SPR change --- src/soc/fu/ldst/loadstore.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py index 22acd797..e3628601 100644 --- a/src/soc/fu/ldst/loadstore.py +++ b/src/soc/fu/ldst/loadstore.py @@ -212,6 +212,7 @@ class LoadStore1(PortInterfaceBase): comb += exception.eq(1) sync += self.state.eq(State.IDLE) sync += ldst_r.eq(0) + sync += Display("cache error -> update dsisr") sync += self.dsisr[63 - 38].eq(~self.load) # XXX there is no architected bit for this # (probably should be a machine check in fact) @@ -254,6 +255,7 @@ class LoadStore1(PortInterfaceBase): with m.If(m_in.err): # MMU RADIX exception thrown comb += exception.eq(1) + sync += Display("MMU RADIX exception thrown") sync += self.dsisr[63 - 33].eq(m_in.invalid) sync += self.dsisr[63 - 36].eq(m_in.perm_error) sync += self.dsisr[63 - 38].eq(self.load) @@ -266,6 +268,7 @@ class LoadStore1(PortInterfaceBase): # alignment error: store address in DAR with m.If(self.align_intr): comb += exc.happened.eq(1) + sync += Display("alignment error: store address in DAR %x", self.addr) sync += self.dar.eq(self.addr) # happened, alignment, instr_fault, invalid. -- 2.30.2