From d21099f764b91af91ffe008a62e03bc37c64229c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 15 Sep 2012 22:29:50 +0200 Subject: [PATCH] examples/de1 : add ramp / square mode --- examples/de1/client/test_MigLa.py | 10 ++++--- examples/de1/top.py | 50 +++++++++++++++++++++++++++++-- 2 files changed, 53 insertions(+), 7 deletions(-) diff --git a/examples/de1/client/test_MigLa.py b/examples/de1/client/test_MigLa.py index d89c41e2..e5dbb893 100644 --- a/examples/de1/client/test_MigLa.py +++ b/examples/de1/client/test_MigLa.py @@ -22,7 +22,7 @@ trig_width = 16 dat_width = 16 # Record Size -record_size = 1024 +record_size = 4096 # Csr Addr MIGIO0_ADDR = 0x0000 @@ -45,13 +45,15 @@ recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size, csr) #============================================================================== # T E S T M I G L A #============================================================================== -term0.write(0x005A) +term0.write(0x0000) sum_tt = gen_truth_table("term0") trigger0.sum.write(sum_tt) +csr.write(0x0000,0) + recorder0.reset() -recorder0.size(256) +recorder0.size(1024) recorder0.offset(0) recorder0.arm() print("-Recorder [Armed]") @@ -62,7 +64,7 @@ print("[Done]") print("-Receiving Data...", end = ' ') sys.stdout.flush() -dat_vcd = recorder0.read(256) +dat_vcd = recorder0.read(1024) print("[Done]") myvcd = Vcd() diff --git a/examples/de1/top.py b/examples/de1/top.py index 39c106a2..41480cf0 100644 --- a/examples/de1/top.py +++ b/examples/de1/top.py @@ -62,7 +62,7 @@ trig_width = 16 dat_width = 16 # Record Size -record_size = 1024 +record_size = 4096 # Csr Addr MIGIO_ADDR = 0x0000 @@ -98,11 +98,55 @@ def get(): comb = [] sync = [] + # # Signal Generator - sig_gen = Signal(BV(trig_width)) + # + + # Counter + cnt_gen = Signal(BV(8)) + sync += [ + cnt_gen.eq(cnt_gen+1) + ] + + # Square + square_gen = Signal(BV(8)) + sync += [ + If(cnt_gen[7], + square_gen.eq(255) + ).Else( + square_gen.eq(0) + ) + ] + + + # Signal Selection + sig_gen = Signal(BV(8)) + comb += [ + If(migIo0.o == 0, + sig_gen.eq(cnt_gen) + ).Elif(migIo0.o == 1, + sig_gen.eq(square_gen) + ).Else( + sig_gen.eq(0) + ) + ] + + ramp_gen = Signal(BV(8)) sync += [ - sig_gen.eq(sig_gen+1) + ramp_gen.eq(ramp_gen+1) ] + + square_gen = Signal(BV(8)) + sync += [ + + ramp_gen.eq(ramp_gen+1) + ] + + + + + + #comb += [sig_gen.eq(migIo0.o)] # Led -- 2.30.2