From d212d7ce66f792f7e940c2272c705d3fdae0f835 Mon Sep 17 00:00:00 2001 From: Shriya Sharma Date: Tue, 26 Sep 2023 11:52:57 +0100 Subject: [PATCH] Added english language description, spaces and brackets for lwaux instruction --- openpower/isa/fixedload.mdwn | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn index 5ade4063..a4e29c6b 100644 --- a/openpower/isa/fixedload.mdwn +++ b/openpower/isa/fixedload.mdwn @@ -471,6 +471,17 @@ Pseudo-code: RT <- EXTS(MEM(EA, 4)) RA <- EA +Description: + + Let the effective address (EA) be the sum (RA)+ (RB). + The word in storage addressed by EA is loaded into + RT[32:63]. RT[0:31] are filled with a copy of bit 0 of the + loaded word. + + EA is placed into register RA. + + If RA=0 or RA=RT, the instruction form is invalid. + Special Registers Altered: None -- 2.30.2