From d22c067047d953b606c8bef3933d5662305f06af Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 2 Apr 2020 15:40:10 +0100 Subject: [PATCH] missing whitespace --- openpower/isa/bcd.mdwn | 3 +++ openpower/isa/fixedload.mdwn | 27 +++++++++++++++++++++++++++ openpower/isa/fixedstore.mdwn | 21 +++++++++++++++++++++ openpower/isa/fixedtrap.mdwn | 5 +++++ openpower/isa/sprset.mdwn | 8 ++++++++ openpower/isa/stringldst.mdwn | 4 ++++ 6 files changed, 68 insertions(+) diff --git a/openpower/isa/bcd.mdwn b/openpower/isa/bcd.mdwn index f157a12c1..9b196a13b 100644 --- a/openpower/isa/bcd.mdwn +++ b/openpower/isa/bcd.mdwn @@ -11,6 +11,7 @@ X-Form RA[n+20:n+31] <- DPD_TO_BCD( (RS)[n+22:n+31] ) Special Registers Altered: + None # Add and Generate Sixes @@ -25,6 +26,7 @@ XO-Form RT <- (¬c) & 0x6666_6666_6666_6666 Special Registers Altered: + None # Convert Binary Coded Decimal To Declets @@ -40,5 +42,6 @@ X-Form RA[n+22:n+31] <- BCD_TO_DPD( (RS)[n+20:n+31] ) Special Registers Altered: + None diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn index 0afdb5261..bb803516b 100644 --- a/openpower/isa/fixedload.mdwn +++ b/openpower/isa/fixedload.mdwn @@ -10,6 +10,7 @@ D-Form RT <- [0]*56 || MEM(EA, 1) Special Registers Altered: + None # Load Byte and Zero Indexed @@ -24,6 +25,7 @@ X-Form RT <- [0] * 56 || MEM(EA, 1) Special Registers Altered: + None # Load Byte and Zero with Update @@ -37,6 +39,7 @@ D-Form RA <- EA Special Registers Altered: + None # Load Byte and Zero with Update Indexed @@ -50,6 +53,7 @@ X-Form RA <- EA Special Registers Altered: + None # Load Halfword and Zero @@ -64,6 +68,7 @@ D-Form RT <- [0] * 48 || MEM(EA, 2) Special Registers Altered: + None # Load Halfword and Zero Indexed @@ -78,6 +83,7 @@ X-Form RT <- [0] * 48 || MEM(EA, 2) Special Registers Altered: + None # Load Halfword and Zero with Update @@ -91,6 +97,7 @@ D-Form RA <- EA Special Registers Altered: + None # Load Halfword and Zero with Update Indexed @@ -104,6 +111,7 @@ X-Form RA <- EA Special Registers Altered: + None # Load Halfword Algebraic @@ -118,6 +126,7 @@ D-Form RT <- EXTS(MEM(EA, 2)) Special Registers Altered: + None # Load Halfword Algebraic Indexed @@ -132,6 +141,7 @@ X-form RT <- EXTS(MEM(EA, 2)) Special Registers Altered: + None # Load Halfword Algebraic with Update @@ -145,6 +155,7 @@ D-Form RA <- EA Special Registers Altered: + None # Load Halfword Algebraic with Update Indexed @@ -158,6 +169,7 @@ X-form RA <- EA Special Registers Altered: + None # Load Word and Zero @@ -172,6 +184,7 @@ D-Form RT <- [0] * 32 || MEM(EA, 4) Special Registers Altered: + None # Load Word and Zero Indexed @@ -186,6 +199,7 @@ X-form RT <- [0] * 32 || MEM(EA, 4) Special Registers Altered: + None # Load Word and Zero with Update @@ -199,6 +213,7 @@ D-Form RA <- EA Special Registers Altered: + None # Load Word and Zero with Update Indexed @@ -212,6 +227,7 @@ X-form RA <- EA Special Registers Altered: + None # Load Word Algebraic @@ -226,6 +242,7 @@ D-Form RT <- EXTS(MEM(EA, 4)) Special Registers Altered: + None # Load Word Algebraic Indexed @@ -240,6 +257,7 @@ X-form RT <- EXTS(MEM(EA, 4)) Special Registers Altered: + None # Load Word Algebraic with Update Indexed @@ -253,6 +271,7 @@ X-form RA <- EA Special Registers Altered: + None # Load Doubleword @@ -267,6 +286,7 @@ DS-Form RT <- MEM(EA, 8) Special Registers Altered: + None # Load Doubleword Indexed @@ -281,6 +301,7 @@ X-form RT <- MEM(EA, 8) Special Registers Altered: + None # Load Doubleword with Update Indexed @@ -294,6 +315,7 @@ DS-Form RA <- EA Special Registers Altered: + None # Load Doubleword with Update Indexed @@ -307,6 +329,7 @@ X-form RA <- EA Special Registers Altered: + None # Load Quadword @@ -321,6 +344,7 @@ DQ-Form RTp <- MEM(EA, 16) Special Registers Altered: + None # Load Halfword Byte-Reverse Indexed @@ -336,6 +360,7 @@ X-form RT <- [0]*48 || load_data[8:15] || load_data[0:7] Special Registers Altered: + None # Load Word Byte-Reverse Indexed @@ -352,6 +377,7 @@ X-form || load_data[8:15] || load_data[0:7] Special Registers Altered: + None # Load Doubleword Byte-Reverse Indexed @@ -370,6 +396,7 @@ X-form || load_data[8:15 || load_data[0:7] Special Registers Altered: + None # Load Multiple Word diff --git a/openpower/isa/fixedstore.mdwn b/openpower/isa/fixedstore.mdwn index 0b94f8ec5..577ac54b0 100644 --- a/openpower/isa/fixedstore.mdwn +++ b/openpower/isa/fixedstore.mdwn @@ -10,6 +10,7 @@ D-Form MEM(EA, 1) <- (RS)[56:63] Special Registers Altered: + None # Store Byte Indexed @@ -24,6 +25,7 @@ X-Form MEM(EA, 1) <- (RS)[56:63] Special Registers Altered: + None # Store Byte with Update @@ -37,6 +39,7 @@ D-Form RA <- EA Special Registers Altered: + None # Store Byte with Update Indexed @@ -50,6 +53,7 @@ X-Form RA <- EA Special Registers Altered: + None # Store Halfword @@ -64,6 +68,7 @@ D-Form MEM(EA, 2) <- (RS)[48:63] Special Registers Altered: + None # Store Halfword Indexed @@ -78,6 +83,7 @@ X-Form MEM(EA, 2) <- (RS)[48:63] Special Registers Altered: + None # Store Halfword with Update @@ -91,6 +97,7 @@ D-Form RA <- EA Special Registers Altered: + None # Store Halfword with Update Indexed @@ -104,6 +111,7 @@ X-Form RA <- EA Special Registers Altered: + None # Store Word @@ -118,6 +126,7 @@ D-Form MEM(EA, 4) <- (RS)[32:63] Special Registers Altered: + None # Store Word Indexed @@ -132,6 +141,7 @@ X-Form MEM(EA, 4) <- (RS)[32:63] Special Registers Altered: + None # Store Word with Update @@ -145,6 +155,7 @@ D-Form RA <- EA Special Registers Altered: + None # Store Word with Update Indexed @@ -158,6 +169,7 @@ X-Form RA <- EA Special Registers Altered: + None # Store Doubleword @@ -172,6 +184,7 @@ DS-Form MEM(EA, 8) <- (RS) Special Registers Altered: + None # Store Doubleword Indexed @@ -186,6 +199,7 @@ X-Form MEM(EA, 8) <- (RS) Special Registers Altered: + None # Store Doubleword with Update @@ -199,6 +213,7 @@ MEM(EA, 8) <- (RS) RA <- EA Special Registers Altered: + None # Store Doubleword with Update Indexed @@ -212,6 +227,7 @@ X-Form RA <- EA Special Registers Altered: + None # Store Quadword @@ -226,6 +242,7 @@ DS-Form MEM(EA, 16) <- RSp Special Registers Altered: + None # Store Halfword Byte-Reverse Indexed @@ -240,6 +257,7 @@ X-Form MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55] Special Registers Altered: + None # Store Word Byte-Reverse Indexed @@ -255,6 +273,7 @@ X-Form ||(RS)[32:39] Special Registers Altered: + None # Store Doubleword Byte-Reverse Indexed @@ -272,6 +291,7 @@ X-Form || (RS)[8:15] || (RS)[0:7] Special Registers Altered: + None # Store Multiple Word @@ -290,5 +310,6 @@ D-Form EA <- EA + 4 Special Registers Altered: + None diff --git a/openpower/isa/fixedtrap.mdwn b/openpower/isa/fixedtrap.mdwn index d758e337e..ae30a10fe 100644 --- a/openpower/isa/fixedtrap.mdwn +++ b/openpower/isa/fixedtrap.mdwn @@ -12,6 +12,7 @@ D-Form if (a >u EXTS(SI)) & TO[4] then TRAP Special Registers Altered: + None # Trap Word @@ -29,6 +30,7 @@ X-Form if (a >u b) & TO[4] then TRAP Special Registers Altered: + None D-Form @@ -46,6 +48,7 @@ D-Form if (a >u b) & TO[4] then TRAP Special Registers Altered: + None # Trap Doubleword @@ -63,6 +66,7 @@ X-Form if (a >u b) & TO[4] then TRAP Special Registers Altered: + None # Integer Select @@ -76,5 +80,6 @@ A-Form else RT <- (RB) Special Registers Altered: + None diff --git a/openpower/isa/sprset.mdwn b/openpower/isa/sprset.mdwn index 723ad2693..be9121fbe 100644 --- a/openpower/isa/sprset.mdwn +++ b/openpower/isa/sprset.mdwn @@ -15,6 +15,7 @@ XFX-Form SPR(n) <- (RS) [32:63] Special Registers Altered: + See spec 3.3.17 # Move From Special Purpose Register @@ -34,6 +35,7 @@ XFX-Form RT <- [0]*32 || SPR(n) Special Registers Altered: + None # Move to CR from XER Extended @@ -45,6 +47,7 @@ X-Form CR[4×BF+32:4×BF+35] <- XER[OV] || XER[OV32] || XER[CA] || XER[CA32] Special Registers Altered: + CR field BF # Move To One Condition Register Field @@ -63,6 +66,7 @@ XFX-Form else CR <- undefined Special Registers Altered: + CR field selected by FXM # Move To Condition Register Fields @@ -75,6 +79,7 @@ XFX-Form CR <- ((RS)[32:63] & mask) | (CR & ¬mask) Special Registers Altered: + CR fields selected by mask # Move From One Condition Register Field @@ -94,6 +99,7 @@ XFX-Form RT[4 *n+32:4*n+35] <- CR[4*n+32:4* n+35] Special Registers Altered: + None # Move From Condition Register @@ -105,6 +111,7 @@ XFX-Form RT <- [0]*32 || CR Special Registers Altered: + None # Set Boolean @@ -121,5 +128,6 @@ X-Form RT <- 0x0000_0000_0000_0000 Special Registers Altered: + None diff --git a/openpower/isa/stringldst.mdwn b/openpower/isa/stringldst.mdwn index 7b55b4667..b52219a3f 100644 --- a/openpower/isa/stringldst.mdwn +++ b/openpower/isa/stringldst.mdwn @@ -21,6 +21,7 @@ X-Form n <- n - 1 Special Registers Altered: + None # Load String Word Indexed @@ -48,6 +49,7 @@ X-Form n <- n - 1 Special Registers Altered: + None # Store String Word Immediate @@ -71,6 +73,7 @@ X-Form n <- n - 1 Special Registers Altered: + None # Store String Word Indexed @@ -94,5 +97,6 @@ X-Form n <- n - 1 Special Registers Altered: + None -- 2.30.2