From d23237f46c3f24b25473fe22af306b391c9753d0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 28 Oct 2022 13:23:42 +0100 Subject: [PATCH] overflow condition in dsld and dsrd if RS is non-zero --- openpower/isa/svfixedarith.mdwn | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn index e8232c27..6d82b896 100644 --- a/openpower/isa/svfixedarith.mdwn +++ b/openpower/isa/svfixedarith.mdwn @@ -60,6 +60,9 @@ Pseudo-code: mask <- MASK(64, 63-n) RT <- (v[0:63] & mask) | ((RC) & ¬mask) RS <- v[0:63] & ¬mask + overflow = 0 + if RS != [0]*64: + overflow = 1 Special Registers Altered: @@ -79,6 +82,9 @@ Pseudo-code: mask <- MASK(n, 63) RT <- (v[0:63] & mask) | ((RC) & ¬mask) RS <- v[0:63] & ¬mask + overflow = 0 + if RS != [0]*64: + overflow = 1 Special Registers Altered: -- 2.30.2