From d253adee61ad9f795f872d7dacdeac2f63c4883f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 28 Apr 2015 18:51:40 +0200 Subject: [PATCH] liteeth: use Migen's Packetizer/Depacketizer, remove generic and move etherbone/tty to frontend --- misoclib/com/liteeth/common.py | 8 ++ misoclib/com/liteeth/core/__init__.py | 1 - misoclib/com/liteeth/core/arp/__init__.py | 11 +-- misoclib/com/liteeth/core/icmp/__init__.py | 11 +-- misoclib/com/liteeth/core/ip/__init__.py | 11 +-- misoclib/com/liteeth/core/ip/checksum.py | 1 - misoclib/com/liteeth/core/ip/crossbar.py | 3 +- misoclib/com/liteeth/core/udp/__init__.py | 11 +-- misoclib/com/liteeth/core/udp/crossbar.py | 4 +- .../com/liteeth/{generic => }/crossbar.py | 2 - .../liteeth/example_designs/targets/base.py | 1 - .../example_designs/targets/etherbone.py | 3 +- .../liteeth/example_designs/targets/tty.py | 2 +- .../liteeth/example_designs/targets/udp.py | 1 - misoclib/com/liteeth/frontend/__init__.py | 0 .../{core => frontend}/etherbone/__init__.py | 1 - .../etherbone/dissector/bit.lua | 0 .../etherbone/dissector/etherbone.lua | 0 .../{core => frontend}/etherbone/packet.py | 11 +-- .../{core => frontend}/etherbone/probe.py | 1 - .../{core => frontend}/etherbone/record.py | 11 +-- .../{core => frontend}/etherbone/wishbone.py | 1 - .../{core => frontend}/tty/__init__.py | 1 - misoclib/com/liteeth/generic/__init__.py | 12 --- misoclib/com/liteeth/generic/depacketizer.py | 79 ----------------- misoclib/com/liteeth/generic/packetizer.py | 87 ------------------- misoclib/com/liteeth/mac/__init__.py | 1 - misoclib/com/liteeth/mac/common.py | 13 ++- misoclib/com/liteeth/mac/core/__init__.py | 1 - misoclib/com/liteeth/mac/core/crc.py | 1 - misoclib/com/liteeth/mac/core/gap.py | 2 - misoclib/com/liteeth/mac/core/last_be.py | 1 - misoclib/com/liteeth/mac/core/padding.py | 1 - misoclib/com/liteeth/mac/core/preamble.py | 1 - misoclib/com/liteeth/mac/frontend/sram.py | 1 - misoclib/com/liteeth/mac/frontend/wishbone.py | 1 - misoclib/com/liteeth/phy/__init__.py | 1 - misoclib/com/liteeth/phy/gmii.py | 1 - misoclib/com/liteeth/phy/gmii_mii.py | 1 - misoclib/com/liteeth/phy/mii.py | 1 - misoclib/com/liteeth/phy/sim.py | 1 - misoclib/com/liteeth/test/common.py | 40 +++++---- misoclib/com/liteeth/test/etherbone_tb.py | 2 +- 43 files changed, 65 insertions(+), 279 deletions(-) rename misoclib/com/liteeth/{generic => }/crossbar.py (96%) create mode 100644 misoclib/com/liteeth/frontend/__init__.py rename misoclib/com/liteeth/{core => frontend}/etherbone/__init__.py (96%) rename misoclib/com/liteeth/{core => frontend}/etherbone/dissector/bit.lua (100%) rename misoclib/com/liteeth/{core => frontend}/etherbone/dissector/etherbone.lua (100%) rename misoclib/com/liteeth/{core => frontend}/etherbone/packet.py (91%) rename misoclib/com/liteeth/{core => frontend}/etherbone/probe.py (94%) rename misoclib/com/liteeth/{core => frontend}/etherbone/record.py (94%) rename misoclib/com/liteeth/{core => frontend}/etherbone/wishbone.py (97%) rename misoclib/com/liteeth/{core => frontend}/tty/__init__.py (98%) delete mode 100644 misoclib/com/liteeth/generic/__init__.py delete mode 100644 misoclib/com/liteeth/generic/depacketizer.py delete mode 100644 misoclib/com/liteeth/generic/packetizer.py diff --git a/misoclib/com/liteeth/common.py b/misoclib/com/liteeth/common.py index 0bc1b01c..f933a34e 100644 --- a/misoclib/com/liteeth/common.py +++ b/misoclib/com/liteeth/common.py @@ -12,6 +12,14 @@ from migen.actorlib.fifo import SyncFIFO, AsyncFIFO from migen.actorlib.packet import * from migen.bank.description import * +class Port: + def connect(self, port): + r = [ + Record.connect(self.source, port.sink), + Record.connect(port.source, self.sink) + ] + return r + eth_mtu = 1532 eth_min_len = 46 eth_interpacket_gap = 12 diff --git a/misoclib/com/liteeth/core/__init__.py b/misoclib/com/liteeth/core/__init__.py index 83451316..f789ac7e 100644 --- a/misoclib/com/liteeth/core/__init__.py +++ b/misoclib/com/liteeth/core/__init__.py @@ -1,5 +1,4 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * from misoclib.com.liteeth.mac import LiteEthMAC from misoclib.com.liteeth.core.arp import LiteEthARP from misoclib.com.liteeth.core.ip import LiteEthIP diff --git a/misoclib/com/liteeth/core/arp/__init__.py b/misoclib/com/liteeth/core/arp/__init__.py index 0c8b68a0..b46522a5 100644 --- a/misoclib/com/liteeth/core/arp/__init__.py +++ b/misoclib/com/liteeth/core/arp/__init__.py @@ -1,7 +1,4 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * -from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer -from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer _arp_table_layout = [ ("reply", 1), @@ -11,9 +8,9 @@ _arp_table_layout = [ ] -class LiteEthARPPacketizer(LiteEthPacketizer): +class LiteEthARPPacketizer(Packetizer): def __init__(self): - LiteEthPacketizer.__init__(self, + Packetizer.__init__(self, eth_arp_description(8), eth_mac_description(8), arp_header) @@ -76,9 +73,9 @@ class LiteEthARPTX(Module): ) -class LiteEthARPDepacketizer(LiteEthDepacketizer): +class LiteEthARPDepacketizer(Depacketizer): def __init__(self): - LiteEthDepacketizer.__init__(self, + Depacketizer.__init__(self, eth_mac_description(8), eth_arp_description(8), arp_header) diff --git a/misoclib/com/liteeth/core/icmp/__init__.py b/misoclib/com/liteeth/core/icmp/__init__.py index e1ddeee8..fc3bdff1 100644 --- a/misoclib/com/liteeth/core/icmp/__init__.py +++ b/misoclib/com/liteeth/core/icmp/__init__.py @@ -1,12 +1,9 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * -from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer -from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer -class LiteEthICMPPacketizer(LiteEthPacketizer): +class LiteEthICMPPacketizer(Packetizer): def __init__(self): - LiteEthPacketizer.__init__(self, + Packetizer.__init__(self, eth_icmp_description(8), eth_ipv4_user_description(8), icmp_header) @@ -51,9 +48,9 @@ class LiteEthICMPTX(Module): ) -class LiteEthICMPDepacketizer(LiteEthDepacketizer): +class LiteEthICMPDepacketizer(Depacketizer): def __init__(self): - LiteEthDepacketizer.__init__(self, + Depacketizer.__init__(self, eth_ipv4_user_description(8), eth_icmp_description(8), icmp_header) diff --git a/misoclib/com/liteeth/core/ip/__init__.py b/misoclib/com/liteeth/core/ip/__init__.py index 88a2f3cd..db564aac 100644 --- a/misoclib/com/liteeth/core/ip/__init__.py +++ b/misoclib/com/liteeth/core/ip/__init__.py @@ -1,14 +1,11 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * from misoclib.com.liteeth.core.ip.checksum import * from misoclib.com.liteeth.core.ip.crossbar import * -from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer -from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer -class LiteEthIPV4Packetizer(LiteEthPacketizer): +class LiteEthIPV4Packetizer(Packetizer): def __init__(self): - LiteEthPacketizer.__init__(self, + Packetizer.__init__(self, eth_ipv4_description(8), eth_mac_description(8), ipv4_header) @@ -98,9 +95,9 @@ class LiteEthIPTX(Module): ) -class LiteEthIPV4Depacketizer(LiteEthDepacketizer): +class LiteEthIPV4Depacketizer(Depacketizer): def __init__(self): - LiteEthDepacketizer.__init__(self, + Depacketizer.__init__(self, eth_mac_description(8), eth_ipv4_description(8), ipv4_header) diff --git a/misoclib/com/liteeth/core/ip/checksum.py b/misoclib/com/liteeth/core/ip/checksum.py index 266713b6..34e84676 100644 --- a/misoclib/com/liteeth/core/ip/checksum.py +++ b/misoclib/com/liteeth/core/ip/checksum.py @@ -1,5 +1,4 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * class LiteEthIPV4Checksum(Module): diff --git a/misoclib/com/liteeth/core/ip/crossbar.py b/misoclib/com/liteeth/core/ip/crossbar.py index 6228c9e7..4570f4fe 100644 --- a/misoclib/com/liteeth/core/ip/crossbar.py +++ b/misoclib/com/liteeth/core/ip/crossbar.py @@ -1,6 +1,5 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * -from misoclib.com.liteeth.generic.crossbar import LiteEthCrossbar +from misoclib.com.liteeth.crossbar import LiteEthCrossbar class LiteEthIPV4MasterPort: diff --git a/misoclib/com/liteeth/core/udp/__init__.py b/misoclib/com/liteeth/core/udp/__init__.py index 20bd9ec6..b0f02d55 100644 --- a/misoclib/com/liteeth/core/udp/__init__.py +++ b/misoclib/com/liteeth/core/udp/__init__.py @@ -1,13 +1,10 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * from misoclib.com.liteeth.core.udp.crossbar import * -from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer -from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer -class LiteEthUDPPacketizer(LiteEthPacketizer): +class LiteEthUDPPacketizer(Packetizer): def __init__(self): - LiteEthPacketizer.__init__(self, + Packetizer.__init__(self, eth_udp_description(8), eth_ipv4_user_description(8), udp_header) @@ -52,9 +49,9 @@ class LiteEthUDPTX(Module): ) -class LiteEthUDPDepacketizer(LiteEthDepacketizer): +class LiteEthUDPDepacketizer(Depacketizer): def __init__(self): - LiteEthDepacketizer.__init__(self, + Depacketizer.__init__(self, eth_ipv4_user_description(8), eth_udp_description(8), udp_header) diff --git a/misoclib/com/liteeth/core/udp/crossbar.py b/misoclib/com/liteeth/core/udp/crossbar.py index e0024ed7..16b2b20c 100644 --- a/misoclib/com/liteeth/core/udp/crossbar.py +++ b/misoclib/com/liteeth/core/udp/crossbar.py @@ -1,7 +1,5 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * - -from misoclib.com.liteeth.generic.crossbar import LiteEthCrossbar +from misoclib.com.liteeth.crossbar import LiteEthCrossbar class LiteEthUDPMasterPort: diff --git a/misoclib/com/liteeth/generic/crossbar.py b/misoclib/com/liteeth/crossbar.py similarity index 96% rename from misoclib/com/liteeth/generic/crossbar.py rename to misoclib/com/liteeth/crossbar.py index abde85b3..d2ee22d3 100644 --- a/misoclib/com/liteeth/generic/crossbar.py +++ b/misoclib/com/liteeth/crossbar.py @@ -1,8 +1,6 @@ from collections import OrderedDict from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * - class LiteEthCrossbar(Module): def __init__(self, master_port, dispatch_param): diff --git a/misoclib/com/liteeth/example_designs/targets/base.py b/misoclib/com/liteeth/example_designs/targets/base.py index 6f5f11d6..83b47ff1 100644 --- a/misoclib/com/liteeth/example_designs/targets/base.py +++ b/misoclib/com/liteeth/example_designs/targets/base.py @@ -9,7 +9,6 @@ from misoclib.tools.litescope.frontend.la import LiteScopeLA from misoclib.tools.litescope.core.port import LiteScopeTerm from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII from misoclib.com.liteeth.core import LiteEthUDPIPCore diff --git a/misoclib/com/liteeth/example_designs/targets/etherbone.py b/misoclib/com/liteeth/example_designs/targets/etherbone.py index 7e5d141b..cf6dc51e 100644 --- a/misoclib/com/liteeth/example_designs/targets/etherbone.py +++ b/misoclib/com/liteeth/example_designs/targets/etherbone.py @@ -3,10 +3,9 @@ from misoclib.tools.litescope.frontend.la import LiteScopeLA from misoclib.tools.litescope.core.port import LiteScopeTerm from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * from targets.base import BaseSoC -from misoclib.com.liteeth.core.etherbone import LiteEthEtherbone +from misoclib.com.liteeth.frontend.etherbone import LiteEthEtherbone class EtherboneSoC(BaseSoC): diff --git a/misoclib/com/liteeth/example_designs/targets/tty.py b/misoclib/com/liteeth/example_designs/targets/tty.py index a915c857..a05fee00 100644 --- a/misoclib/com/liteeth/example_designs/targets/tty.py +++ b/misoclib/com/liteeth/example_designs/targets/tty.py @@ -6,7 +6,7 @@ from misoclib.com.liteeth.common import * from misoclib.com.liteeth.generic import * from targets.base import BaseSoC -from misoclib.com.liteeth.core.tty import LiteEthTTY +from misoclib.com.liteeth.frontend.tty import LiteEthTTY class TTYSoC(BaseSoC): diff --git a/misoclib/com/liteeth/example_designs/targets/udp.py b/misoclib/com/liteeth/example_designs/targets/udp.py index 9aea0c23..c793f2a2 100644 --- a/misoclib/com/liteeth/example_designs/targets/udp.py +++ b/misoclib/com/liteeth/example_designs/targets/udp.py @@ -3,7 +3,6 @@ from misoclib.tools.litescope.frontend.la import LiteScopeLA from misoclib.tools.litescope.core.port import LiteScopeTerm from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * from targets.base import BaseSoC diff --git a/misoclib/com/liteeth/frontend/__init__.py b/misoclib/com/liteeth/frontend/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/misoclib/com/liteeth/core/etherbone/__init__.py b/misoclib/com/liteeth/frontend/etherbone/__init__.py similarity index 96% rename from misoclib/com/liteeth/core/etherbone/__init__.py rename to misoclib/com/liteeth/frontend/etherbone/__init__.py index 3c7d6f9a..b2e958f1 100644 --- a/misoclib/com/liteeth/core/etherbone/__init__.py +++ b/misoclib/com/liteeth/frontend/etherbone/__init__.py @@ -1,5 +1,4 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * from misoclib.com.liteeth.core.etherbone.packet import * from misoclib.com.liteeth.core.etherbone.probe import * from misoclib.com.liteeth.core.etherbone.record import * diff --git a/misoclib/com/liteeth/core/etherbone/dissector/bit.lua b/misoclib/com/liteeth/frontend/etherbone/dissector/bit.lua similarity index 100% rename from misoclib/com/liteeth/core/etherbone/dissector/bit.lua rename to misoclib/com/liteeth/frontend/etherbone/dissector/bit.lua diff --git a/misoclib/com/liteeth/core/etherbone/dissector/etherbone.lua b/misoclib/com/liteeth/frontend/etherbone/dissector/etherbone.lua similarity index 100% rename from misoclib/com/liteeth/core/etherbone/dissector/etherbone.lua rename to misoclib/com/liteeth/frontend/etherbone/dissector/etherbone.lua diff --git a/misoclib/com/liteeth/core/etherbone/packet.py b/misoclib/com/liteeth/frontend/etherbone/packet.py similarity index 91% rename from misoclib/com/liteeth/core/etherbone/packet.py rename to misoclib/com/liteeth/frontend/etherbone/packet.py index 2a236d57..e628bd96 100644 --- a/misoclib/com/liteeth/core/etherbone/packet.py +++ b/misoclib/com/liteeth/frontend/etherbone/packet.py @@ -1,12 +1,9 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * -from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer -from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer -class LiteEthEtherbonePacketPacketizer(LiteEthPacketizer): +class LiteEthEtherbonePacketPacketizer(Packetizer): def __init__(self): - LiteEthPacketizer.__init__(self, + Packetizer.__init__(self, eth_etherbone_packet_description(32), eth_udp_user_description(32), etherbone_packet_header) @@ -56,9 +53,9 @@ class LiteEthEtherbonePacketTX(Module): ) -class LiteEthEtherbonePacketDepacketizer(LiteEthDepacketizer): +class LiteEthEtherbonePacketDepacketizer(Depacketizer): def __init__(self): - LiteEthDepacketizer.__init__(self, + Depacketizer.__init__(self, eth_udp_user_description(32), eth_etherbone_packet_description(32), etherbone_packet_header) diff --git a/misoclib/com/liteeth/core/etherbone/probe.py b/misoclib/com/liteeth/frontend/etherbone/probe.py similarity index 94% rename from misoclib/com/liteeth/core/etherbone/probe.py rename to misoclib/com/liteeth/frontend/etherbone/probe.py index 9e9671f7..ade1305d 100644 --- a/misoclib/com/liteeth/core/etherbone/probe.py +++ b/misoclib/com/liteeth/frontend/etherbone/probe.py @@ -1,5 +1,4 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * class LiteEthEtherboneProbe(Module): diff --git a/misoclib/com/liteeth/core/etherbone/record.py b/misoclib/com/liteeth/frontend/etherbone/record.py similarity index 94% rename from misoclib/com/liteeth/core/etherbone/record.py rename to misoclib/com/liteeth/frontend/etherbone/record.py index 263234c4..15879fd2 100644 --- a/misoclib/com/liteeth/core/etherbone/record.py +++ b/misoclib/com/liteeth/frontend/etherbone/record.py @@ -1,20 +1,17 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * -from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer -from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer -class LiteEthEtherboneRecordPacketizer(LiteEthPacketizer): +class LiteEthEtherboneRecordPacketizer(Packetizer): def __init__(self): - LiteEthPacketizer.__init__(self, + Packetizer.__init__(self, eth_etherbone_record_description(32), eth_etherbone_packet_user_description(32), etherbone_record_header) -class LiteEthEtherboneRecordDepacketizer(LiteEthDepacketizer): +class LiteEthEtherboneRecordDepacketizer(Depacketizer): def __init__(self): - LiteEthDepacketizer.__init__(self, + Depacketizer.__init__(self, eth_etherbone_packet_user_description(32), eth_etherbone_record_description(32), etherbone_record_header) diff --git a/misoclib/com/liteeth/core/etherbone/wishbone.py b/misoclib/com/liteeth/frontend/etherbone/wishbone.py similarity index 97% rename from misoclib/com/liteeth/core/etherbone/wishbone.py rename to misoclib/com/liteeth/frontend/etherbone/wishbone.py index fbaf0630..b9b8c3bc 100644 --- a/misoclib/com/liteeth/core/etherbone/wishbone.py +++ b/misoclib/com/liteeth/frontend/etherbone/wishbone.py @@ -1,5 +1,4 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * from migen.bus import wishbone diff --git a/misoclib/com/liteeth/core/tty/__init__.py b/misoclib/com/liteeth/frontend/tty/__init__.py similarity index 98% rename from misoclib/com/liteeth/core/tty/__init__.py rename to misoclib/com/liteeth/frontend/tty/__init__.py index d88d7273..56867af9 100644 --- a/misoclib/com/liteeth/core/tty/__init__.py +++ b/misoclib/com/liteeth/frontend/tty/__init__.py @@ -1,5 +1,4 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * class LiteEthTTYTX(Module): diff --git a/misoclib/com/liteeth/generic/__init__.py b/misoclib/com/liteeth/generic/__init__.py deleted file mode 100644 index 71d0d077..00000000 --- a/misoclib/com/liteeth/generic/__init__.py +++ /dev/null @@ -1,12 +0,0 @@ -from migen.fhdl.decorators import ModuleTransformer -from misoclib.com.liteeth.common import * - - -# Generic classes -class Port: - def connect(self, port): - r = [ - Record.connect(self.source, port.sink), - Record.connect(port.source, self.sink) - ] - return r diff --git a/misoclib/com/liteeth/generic/depacketizer.py b/misoclib/com/liteeth/generic/depacketizer.py deleted file mode 100644 index 20a85bb0..00000000 --- a/misoclib/com/liteeth/generic/depacketizer.py +++ /dev/null @@ -1,79 +0,0 @@ -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * - - -class LiteEthDepacketizer(Module): - def __init__(self, sink_description, source_description, header): - self.sink = sink = Sink(sink_description) - self.source = source = Source(source_description) - self.header = Signal(header.length*8) - - # # # - - dw = flen(sink.data) - - header_words = (header.length*8)//dw - - shift = Signal() - counter = Counter(max=max(header_words, 2)) - self.submodules += counter - - if header_words == 1: - self.sync += \ - If(shift, - self.header.eq(sink.data) - ) - else: - self.sync += \ - If(shift, - self.header.eq(Cat(self.header[dw:], sink.data)) - ) - - fsm = FSM(reset_state="IDLE") - self.submodules += fsm - - if header_words == 1: - idle_next_state = "COPY" - else: - idle_next_state = "RECEIVE_HEADER" - - fsm.act("IDLE", - sink.ack.eq(1), - counter.reset.eq(1), - If(sink.stb, - shift.eq(1), - NextState(idle_next_state) - ) - ) - if header_words != 1: - fsm.act("RECEIVE_HEADER", - sink.ack.eq(1), - If(sink.stb, - counter.ce.eq(1), - shift.eq(1), - If(counter.value == header_words-2, - NextState("COPY") - ) - ) - ) - no_payload = Signal() - self.sync += \ - If(fsm.before_entering("COPY"), - source.sop.eq(1), - no_payload.eq(sink.eop) - ).Elif(source.stb & source.ack, - source.sop.eq(0) - ) - self.comb += [ - source.eop.eq(sink.eop | no_payload), - source.data.eq(sink.data), - source.error.eq(sink.error), - header.decode(self.header, source) - ] - fsm.act("COPY", - sink.ack.eq(source.ack), - source.stb.eq(sink.stb | no_payload), - If(source.stb & source.ack & source.eop, - NextState("IDLE") - ) - ) diff --git a/misoclib/com/liteeth/generic/packetizer.py b/misoclib/com/liteeth/generic/packetizer.py deleted file mode 100644 index 23a83c2a..00000000 --- a/misoclib/com/liteeth/generic/packetizer.py +++ /dev/null @@ -1,87 +0,0 @@ -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * - - -class LiteEthPacketizer(Module): - def __init__(self, sink_description, source_description, header): - self.sink = sink = Sink(sink_description) - self.source = source = Source(source_description) - self.header = Signal(header.length*8) - - # # # - - dw = flen(self.sink.data) - - header_reg = Signal(header.length*8) - header_words = (header.length*8)//dw - load = Signal() - shift = Signal() - counter = Counter(max=max(header_words, 2)) - self.submodules += counter - - self.comb += header.encode(sink, self.header) - if header_words == 1: - self.sync += [ - If(load, - header_reg.eq(self.header) - ) - ] - else: - self.sync += [ - If(load, - header_reg.eq(self.header) - ).Elif(shift, - header_reg.eq(Cat(header_reg[dw:], Signal(dw))) - ) - ] - - fsm = FSM(reset_state="IDLE") - self.submodules += fsm - - if header_words == 1: - idle_next_state = "COPY" - else: - idle_next_state = "SEND_HEADER" - - fsm.act("IDLE", - sink.ack.eq(1), - counter.reset.eq(1), - If(sink.stb & sink.sop, - sink.ack.eq(0), - source.stb.eq(1), - source.sop.eq(1), - source.eop.eq(0), - source.data.eq(self.header[:dw]), - If(source.stb & source.ack, - load.eq(1), - NextState(idle_next_state) - ) - ) - ) - if header_words != 1: - fsm.act("SEND_HEADER", - source.stb.eq(1), - source.sop.eq(0), - source.eop.eq(0), - source.data.eq(header_reg[dw:2*dw]), - If(source.stb & source.ack, - shift.eq(1), - counter.ce.eq(1), - If(counter.value == header_words-2, - NextState("COPY") - ) - ) - ) - fsm.act("COPY", - source.stb.eq(sink.stb), - source.sop.eq(0), - source.eop.eq(sink.eop), - source.data.eq(sink.data), - source.error.eq(sink.error), - If(source.stb & source.ack, - sink.ack.eq(1), - If(source.eop, - NextState("IDLE") - ) - ) - ) diff --git a/misoclib/com/liteeth/mac/__init__.py b/misoclib/com/liteeth/mac/__init__.py index f951c38b..5c2a0675 100644 --- a/misoclib/com/liteeth/mac/__init__.py +++ b/misoclib/com/liteeth/mac/__init__.py @@ -1,5 +1,4 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * from misoclib.com.liteeth.mac.common import * from misoclib.com.liteeth.mac.core import LiteEthMACCore from misoclib.com.liteeth.mac.frontend.wishbone import LiteEthMACWishboneInterface diff --git a/misoclib/com/liteeth/mac/common.py b/misoclib/com/liteeth/mac/common.py index 809ad4fb..f12cc3e7 100644 --- a/misoclib/com/liteeth/mac/common.py +++ b/misoclib/com/liteeth/mac/common.py @@ -1,21 +1,18 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * -from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer -from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer -from misoclib.com.liteeth.generic.crossbar import LiteEthCrossbar +from misoclib.com.liteeth.crossbar import LiteEthCrossbar -class LiteEthMACDepacketizer(LiteEthDepacketizer): +class LiteEthMACDepacketizer(Depacketizer): def __init__(self): - LiteEthDepacketizer.__init__(self, + Depacketizer.__init__(self, eth_phy_description(8), eth_mac_description(8), mac_header) -class LiteEthMACPacketizer(LiteEthPacketizer): +class LiteEthMACPacketizer(Packetizer): def __init__(self): - LiteEthPacketizer.__init__(self, + Packetizer.__init__(self, eth_mac_description(8), eth_phy_description(8), mac_header) diff --git a/misoclib/com/liteeth/mac/core/__init__.py b/misoclib/com/liteeth/mac/core/__init__.py index 7322c42f..f8b18f73 100644 --- a/misoclib/com/liteeth/mac/core/__init__.py +++ b/misoclib/com/liteeth/mac/core/__init__.py @@ -1,5 +1,4 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * from misoclib.com.liteeth.mac.core import gap, preamble, crc, padding, last_be from misoclib.com.liteeth.phy.sim import LiteEthPHYSim diff --git a/misoclib/com/liteeth/mac/core/crc.py b/misoclib/com/liteeth/mac/core/crc.py index d3549791..ba7c5319 100644 --- a/misoclib/com/liteeth/mac/core/crc.py +++ b/misoclib/com/liteeth/mac/core/crc.py @@ -1,5 +1,4 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * class LiteEthMACCRCEngine(Module): diff --git a/misoclib/com/liteeth/mac/core/gap.py b/misoclib/com/liteeth/mac/core/gap.py index d4caf3c6..c1bd9162 100644 --- a/misoclib/com/liteeth/mac/core/gap.py +++ b/misoclib/com/liteeth/mac/core/gap.py @@ -1,6 +1,4 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * - class LiteEthMACGap(Module): def __init__(self, dw, ack_on_gap=False): diff --git a/misoclib/com/liteeth/mac/core/last_be.py b/misoclib/com/liteeth/mac/core/last_be.py index 29844f38..42f7c641 100644 --- a/misoclib/com/liteeth/mac/core/last_be.py +++ b/misoclib/com/liteeth/mac/core/last_be.py @@ -1,5 +1,4 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * class LiteEthMACTXLastBE(Module): diff --git a/misoclib/com/liteeth/mac/core/padding.py b/misoclib/com/liteeth/mac/core/padding.py index 7874d874..38b2a3da 100644 --- a/misoclib/com/liteeth/mac/core/padding.py +++ b/misoclib/com/liteeth/mac/core/padding.py @@ -1,5 +1,4 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * class LiteEthMACPaddingInserter(Module): diff --git a/misoclib/com/liteeth/mac/core/preamble.py b/misoclib/com/liteeth/mac/core/preamble.py index 2854fab9..18e86f83 100644 --- a/misoclib/com/liteeth/mac/core/preamble.py +++ b/misoclib/com/liteeth/mac/core/preamble.py @@ -1,5 +1,4 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * class LiteEthMACPreambleInserter(Module): diff --git a/misoclib/com/liteeth/mac/frontend/sram.py b/misoclib/com/liteeth/mac/frontend/sram.py index 3a6a8c29..fc3d8c27 100644 --- a/misoclib/com/liteeth/mac/frontend/sram.py +++ b/misoclib/com/liteeth/mac/frontend/sram.py @@ -1,5 +1,4 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * from migen.bank.description import * from migen.bank.eventmanager import * diff --git a/misoclib/com/liteeth/mac/frontend/wishbone.py b/misoclib/com/liteeth/mac/frontend/wishbone.py index 5b9d5563..91c227f1 100644 --- a/misoclib/com/liteeth/mac/frontend/wishbone.py +++ b/misoclib/com/liteeth/mac/frontend/wishbone.py @@ -1,5 +1,4 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * from misoclib.com.liteeth.mac.frontend import sram from migen.bus import wishbone diff --git a/misoclib/com/liteeth/phy/__init__.py b/misoclib/com/liteeth/phy/__init__.py index d06352ac..16413b9b 100644 --- a/misoclib/com/liteeth/phy/__init__.py +++ b/misoclib/com/liteeth/phy/__init__.py @@ -1,5 +1,4 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * def LiteEthPHY(clock_pads, pads, **kwargs): diff --git a/misoclib/com/liteeth/phy/gmii.py b/misoclib/com/liteeth/phy/gmii.py index 998522b3..cdf07180 100644 --- a/misoclib/com/liteeth/phy/gmii.py +++ b/misoclib/com/liteeth/phy/gmii.py @@ -1,7 +1,6 @@ from migen.genlib.io import DDROutput from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * class LiteEthPHYGMIITX(Module): diff --git a/misoclib/com/liteeth/phy/gmii_mii.py b/misoclib/com/liteeth/phy/gmii_mii.py index d1bd7d7f..ec3e5855 100644 --- a/misoclib/com/liteeth/phy/gmii_mii.py +++ b/misoclib/com/liteeth/phy/gmii_mii.py @@ -3,7 +3,6 @@ from migen.flow.plumbing import Multiplexer, Demultiplexer from migen.genlib.cdc import PulseSynchronizer from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMIICRG from misoclib.com.liteeth.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX diff --git a/misoclib/com/liteeth/phy/mii.py b/misoclib/com/liteeth/phy/mii.py index 5f121cdf..e687e763 100644 --- a/misoclib/com/liteeth/phy/mii.py +++ b/misoclib/com/liteeth/phy/mii.py @@ -1,5 +1,4 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * def converter_description(dw): diff --git a/misoclib/com/liteeth/phy/sim.py b/misoclib/com/liteeth/phy/sim.py index d4067b3e..eda52d6e 100644 --- a/misoclib/com/liteeth/phy/sim.py +++ b/misoclib/com/liteeth/phy/sim.py @@ -1,7 +1,6 @@ import os from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * class LiteEthPHYSimCRG(Module, AutoCSR): diff --git a/misoclib/com/liteeth/test/common.py b/misoclib/com/liteeth/test/common.py index 4f72b6fa..716443c3 100644 --- a/misoclib/com/liteeth/test/common.py +++ b/misoclib/com/liteeth/test/common.py @@ -108,19 +108,21 @@ class PacketStreamer(Module): self.packet = self.packets.pop(0) if not self.packet.ongoing and not self.packet.done: selfp.source.stb = 1 - selfp.source.sop = 1 + if self.source.description.packetized: + selfp.source.sop = 1 selfp.source.data = self.packet.pop(0) self.packet.ongoing = True elif selfp.source.stb == 1 and selfp.source.ack == 1: - selfp.source.sop = 0 - if len(self.packet) == 1: - selfp.source.eop = 1 - if self.last_be is not None: - selfp.source.last_be = self.last_be - else: - selfp.source.eop = 0 - if self.last_be is not None: - selfp.source.last_be = 0 + if self.source.description.packetized: + selfp.source.sop = 0 + if len(self.packet) == 1: + selfp.source.eop = 1 + if self.last_be is not None: + selfp.source.last_be = self.last_be + else: + selfp.source.eop = 0 + if self.last_be is not None: + selfp.source.last_be = 0 if len(self.packet) > 0: selfp.source.stb = 1 selfp.source.data = self.packet.pop(0) @@ -144,13 +146,17 @@ class PacketLogger(Module): def do_simulation(self, selfp): selfp.sink.ack = 1 - if selfp.sink.stb == 1 and selfp.sink.sop == 1: - self.packet = Packet() - self.packet.append(selfp.sink.data) - elif selfp.sink.stb: - self.packet.append(selfp.sink.data) - if selfp.sink.stb == 1 and selfp.sink.eop == 1: - self.packet.done = True + if selfp.sink.stb: + if self.sink.description.packetized: + if selfp.sink.sop: + self.packet = Packet() + self.packet.append(selfp.sink.data) + else: + self.packet.append(selfp.sink.data) + if selfp.sink.eop: + self.packet.done = True + else: + self.packet.append(selfp.sink.data) class AckRandomizer(Module): diff --git a/misoclib/com/liteeth/test/etherbone_tb.py b/misoclib/com/liteeth/test/etherbone_tb.py index c070a32b..8f868474 100644 --- a/misoclib/com/liteeth/test/etherbone_tb.py +++ b/misoclib/com/liteeth/test/etherbone_tb.py @@ -5,7 +5,7 @@ from migen.sim.generic import run_simulation from misoclib.com.liteeth.common import * from misoclib.com.liteeth.core import LiteEthUDPIPCore -from misoclib.com.liteeth.core.etherbone import LiteEthEtherbone +from misoclib.com.liteeth.frontend.etherbone import LiteEthEtherbone from misoclib.com.liteeth.test.common import * from misoclib.com.liteeth.test.model import phy, mac, arp, ip, udp, etherbone -- 2.30.2