From d25b9804b5343a6a1546418a2650d0e838280558 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 28 Mar 2021 14:37:16 +0100 Subject: [PATCH] reduce number of regfile ports --- src/soc/simple/core.py | 21 +++++++++++++-------- src/soc/simple/test/test_runner.py | 1 + 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 298c9d87..7b2e7b8d 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -71,6 +71,10 @@ class NonProductionCore(Elaboratable): def __init__(self, pspec): self.pspec = pspec + # test to see if regfile ports should be reduced + self.regreduce_en = (hasattr(pspec, "regreduce") and + (pspec.regreduce_en == True)) + # single LD/ST funnel for memory access self.l0 = TstL0CacheBuffer(pspec, n_units=1) pi = self.l0.l0.dports[0] @@ -339,14 +343,15 @@ class NonProductionCore(Elaboratable): # argh. an experiment to merge RA and RB in the INT regfile # (we have too many read/write ports) - #if regfile == 'INT': - #fuspecs['rabc'] = [fuspecs.pop('rb')] - #fuspecs['rabc'].append(fuspecs.pop('rc')) - #fuspecs['rabc'].append(fuspecs.pop('ra')) - #if regfile == 'FAST': - # fuspecs['fast1'] = [fuspecs.pop('fast1')] - # if 'fast2' in fuspecs: - # fuspecs['fast1'].append(fuspecs.pop('fast2')) + if self.regreduce_en: + if regfile == 'INT': + fuspecs['rabc'] = [fuspecs.pop('rb')] + fuspecs['rabc'].append(fuspecs.pop('rc')) + fuspecs['rabc'].append(fuspecs.pop('ra')) + if regfile == 'FAST': + fuspecs['fast1'] = [fuspecs.pop('fast1')] + if 'fast2' in fuspecs: + fuspecs['fast1'].append(fuspecs.pop('fast2')) # for each named regfile port, connect up all FUs to that port for (regname, fspec) in sort_fuspecs(fuspecs): diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index 75c95742..fd912bed 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -145,6 +145,7 @@ class TestRunner(FHDLTestCase): nocore=False, xics=False, gpio=False, + regreduce=True, svp64=self.svp64, mmu=self.microwatt_mmu, reg_wid=64) -- 2.30.2