From d25b9dca4850f9dd648324514c007926ed00bb08 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 2 Oct 2022 17:43:28 +0100 Subject: [PATCH] --- openpower/sv/biginteger.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn index 83122ee50..1b0817751 100644 --- a/openpower/sv/biginteger.mdwn +++ b/openpower/sv/biginteger.mdwn @@ -31,7 +31,7 @@ for subtraction) but that big-integer shift, multiply and divide require an extra 3-in 2-out instructions, similar to Intel's [shld](https://www.felixcloutier.com/x86/shld) and [shrd](https://www.felixcloutier.com/x86/shrd), -`mulx` and `idiv`, to be efficient. +`mulx` and `divq`, to be efficient. The same instruction (`maddedu`) is used in both big-divide and big-multiply because 'maddedu''s primary purpose is to perform a fused 64-bit scalar multiply with a large vector, @@ -138,7 +138,7 @@ that is near-identical to `divdeu` except that: RB, the divisor, remains 64 bit. The instruction is therefore a 128/64 division, producing a (pair) of 64 bit result(s), in the same way that -Intel [idiv](https://www.felixcloutier.com/x86/idiv) works. +Intel [divq](https://www.felixcloutier.com/x86/div) works. Overflow conditions are detected in exactly the same fashion as `divdeu`, except that rather than have `UNDEFINED` behaviour, RT is set to all ones and RS set to all -- 2.30.2