From d27425407c98966e65c05ef46cca97f76acd4649 Mon Sep 17 00:00:00 2001 From: Staf Verhaegen Date: Thu, 26 Mar 2020 21:08:04 +0100 Subject: [PATCH] Re: [libre-riscv-dev] cache SRAM organisation --- f1/deb7ace55d10ebde8222b4a9f1decb3472c9d6 | 97 +++++++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 f1/deb7ace55d10ebde8222b4a9f1decb3472c9d6 diff --git a/f1/deb7ace55d10ebde8222b4a9f1decb3472c9d6 b/f1/deb7ace55d10ebde8222b4a9f1decb3472c9d6 new file mode 100644 index 0000000..3b95f1e --- /dev/null +++ b/f1/deb7ace55d10ebde8222b4a9f1decb3472c9d6 @@ -0,0 +1,97 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Thu, 26 Mar 2020 20:08:13 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jHYnU-0004Vy-4N; Thu, 26 Mar 2020 20:08:12 +0000 +Received: from vps2.stafverhaegen.be ([85.10.201.15]) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) id 1jHYnS-0004Vs-UG + for libre-riscv-dev@lists.libre-riscv.org; Thu, 26 Mar 2020 20:08:10 +0000 +Received: from hpdc7800 (hpdc7800 [10.0.0.1]) + by vps2.stafverhaegen.be (Postfix) with ESMTP id 392FD11C0287 + for ; + Thu, 26 Mar 2020 21:08:10 +0100 (CET) +Message-ID: <7b5a312befec67dbf14d31f5bb4c418c8784e787.camel@fibraservi.eu> +From: Staf Verhaegen +To: libre-riscv-dev@lists.libre-riscv.org +Date: Thu, 26 Mar 2020 21:08:04 +0100 +In-Reply-To: +References: + <29b1a9ecedda151dc9c8da6516c3691dfede62ef.camel@fibraservi.eu> + + <6fa40cb78b3f8c013ca4953ccb4daa5c23e3b501.camel@fibraservi.eu> + + + +Organization: FibraServi bvba +X-Mailer: Evolution 3.28.5 (3.28.5-5.el7) +Mime-Version: 1.0 +X-Content-Filtered-By: Mailman/MimeDel 2.1.23 +Subject: Re: [libre-riscv-dev] cache SRAM organisation +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: multipart/mixed; boundary="===============4555861804105343232==" +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + + +--===============4555861804105343232== +Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; + boundary="=-nceve67+MkGTTWulbZUI" + + +--=-nceve67+MkGTTWulbZUI +Content-Type: text/plain; charset="UTF-8" +Content-Transfer-Encoding: quoted-printable + +Luke Kenneth Casson Leighton schreef op do 26-03-2020 om 15:15 [+0000]: +> On Thursday, March 26, 2020, Staf Verhaegen wrote: +> > I can understand you do this to implement functional units withconfigur= +able pipeline length but I would strongly discourage to pipelineregister fi= +les after each other . +>=20 +>=20 +> "pipeline register files after each other"? apologies i am not clear what= +you mean, here. do you mean "don't do write-thru on the Regfile"? + +No I meant for example connecting the output of one port of an asynchronous= + RAM to for example the address input of another port of an asynchronous RA= +M. + +greets, +Staf. + + +--=-nceve67+MkGTTWulbZUI-- + + + +--===============4555861804105343232== +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: base64 +Content-Disposition: inline + +X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlicmUtcmlz +Y3YtZGV2IG1haWxpbmcgbGlzdApsaWJyZS1yaXNjdi1kZXZAbGlzdHMubGlicmUtcmlzY3Yub3Jn +Cmh0dHA6Ly9saXN0cy5saWJyZS1yaXNjdi5vcmcvbWFpbG1hbi9saXN0aW5mby9saWJyZS1yaXNj +di1kZXYK + +--===============4555861804105343232==-- + + + -- 2.30.2