From d280723618b8a75c7f6a0d283c89b0fc43410af4 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 8 Jun 2012 14:00:49 +0200 Subject: [PATCH] examples/fir: print Verilog source --- examples/fir.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/examples/fir.py b/examples/fir.py index e10ff94e..2119679f 100644 --- a/examples/fir.py +++ b/examples/fir.py @@ -76,5 +76,9 @@ def main(): plt.plot(in_signals) plt.plot(out_signals) plt.show() + + # Print the Verilog source for the filter. + print(verilog.convert(fir.get_fragment(), + ios={fir.i, fir.o})) main() -- 2.30.2