From d2a8eba72bb8b43a5d4676c8ed880742c0402087 Mon Sep 17 00:00:00 2001 From: "colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0" Date: Fri, 9 Apr 2021 21:48:03 +0100 Subject: [PATCH] --- HDL_workflow/ECP5_FPGA.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn index fa61e6da1..ae8d70bd4 100644 --- a/HDL_workflow/ECP5_FPGA.mdwn +++ b/HDL_workflow/ECP5_FPGA.mdwn @@ -163,8 +163,9 @@ Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) | Label As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs. +ft232 pin and wire colour table converted to jtag signal names: -``` ft232 pin and wire colour table converted to jtag signal names +``` _________________________ | Pin # | Name | Colour | |-------|------|----------| -- 2.30.2