From d2b069516a6c38e57bf649b050e09e1c827fede0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 10 Feb 2020 14:48:46 +0100 Subject: [PATCH] soc: add cpu rom/sram check --- litex/soc/integration/soc.py | 9 +++++++++ litex/soc/integration/soc_core.py | 6 ------ 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 696375f0..eb2cfbbb 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -816,6 +816,15 @@ class SoC(Module): masters = list(self.csr.masters.values()), slaves = self.csr_bankarray.get_buses()) + # SoC CPU Check ---------------------------------------------------------------------------- + if not isinstance(self.cpu, cpu.CPUNone): + for name in ["rom", "sram"]: + if name not in list(self.bus.regions.keys()) + list(self.bus.ld_regions.keys()): + self.logger.error("CPU needs {} Region to be defined as Bus or Linker Region.".format( + colorer(name, color="red"))) + self.logger.error(self.bus) + raise + # SoC IRQ Interconnect --------------------------------------------------------------------- if hasattr(self, "cpu"): if hasattr(self.cpu, "interrupt"): diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 5417479c..5f9c2e29 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -202,12 +202,6 @@ class SoCCore(SoC): region.length = region.size region.type = "cached" if region.cached else "io" - # Verify CPU has required memories - if not isinstance(self.cpu, cpu.CPUNone): - for name in ["rom", "sram"]: - if name not in self.bus.regions.keys(): - raise FinalizeError("CPU needs \"{}\" to be defined as memory or linker region".format(name)) - SoC.do_finalize(self) # Add CSRs regions -- 2.30.2