From d2c33863d08bbc506888b723a304aa11f8650296 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 31 Jul 2019 16:04:19 -0700 Subject: [PATCH] Do not compute sign bit if result is zero --- techlibs/common/mul2dsp.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index b745547a8..bfd216fbf 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -69,7 +69,6 @@ module \$mul (A, B, Y); ); else if (A_SIGNED && (A_WIDTH > `DSP_A_MAXWIDTH || B_WIDTH > `DSP_B_MAXWIDTH)) begin wire _; - assign Y[Y_WIDTH-1] = A[A_WIDTH-1] ^ B[B_WIDTH-1]; \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), @@ -81,6 +80,8 @@ module \$mul (A, B, Y); .B(B), .Y({_,Y[Y_WIDTH-2:0]}) ); + // For non-zero results, recompute sign bit + assign Y[Y_WIDTH-1] = (|Y[Y_WIDTH-2:0]) & (A[A_WIDTH-1] ^ B[B_WIDTH-1]); end else \$__mul #( -- 2.30.2