From d2ce266cbafc97b1da6b7491043de80fe2e85889 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 21 Jan 2015 10:52:18 +0100 Subject: [PATCH] fix core generation --- targets/core.py | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/targets/core.py b/targets/core.py index 4746557b..1f0072e9 100644 --- a/targets/core.py +++ b/targets/core.py @@ -7,11 +7,6 @@ from litesata import LiteSATA class _CRG(Module): def __init__(self, platform): self.cd_sys = ClockDomain() - self.reset = Signal() - self.comb += self.cd_sys.clk.eq(platform.request("sys_clk")) - self.specials += [ - AsyncResetSynchronizer(self.cd_sys, platform.request("sys_rst") | self.reset), - ] class LiteSATACore(Module): default_platform = "verilog_backend" @@ -22,11 +17,10 @@ class LiteSATACore(Module): # SATA PHY/Core/Frontend self.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "SATA2", clk_freq) - self.comb += self.crg.reset.eq(self.sata_phy.ctrl.need_reset) # XXX FIXME self.sata = LiteSATA(self.sata_phy, with_crossbar=True) # Get user ports from crossbar - n = 4 + n = 1 self.crossbar_ports = self.sata.crossbar.get_ports(n) def get_ios(self): -- 2.30.2