From d2ef72441cec8cfb077f69e409da23461d2e0850 Mon Sep 17 00:00:00 2001 From: Shriya Sharma Date: Fri, 27 Oct 2023 11:35:47 +0100 Subject: [PATCH] added english language description for lwasux instruction --- openpower/isa/fixedloadshift.mdwn | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn index 291fcfc2..4415ebff 100644 --- a/openpower/isa/fixedloadshift.mdwn +++ b/openpower/isa/fixedloadshift.mdwn @@ -270,6 +270,18 @@ Pseudo-code: RT <- EXTS(MEM(EA, 4)) RA <- EA +Description: + + Let the effective address (EA) be the sum of the contents of + register RB shifted by (SH+1), and (RA). + + The word in storage addressed by EA is loaded into RT[32:63]. + RT[0:31] are filled with a copy of bit 0 of the loaded word. + + EA is placed into register RA. + + If RA=0 or RA=RT, the instruction form is invalid. + Special Registers Altered: None -- 2.30.2