From d2f76495c94d6fa9c447eab77d2758830b35a7d9 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 19 Apr 2023 17:43:37 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls013.mdwn | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/openpower/sv/rfc/ls013.mdwn b/openpower/sv/rfc/ls013.mdwn index 2d479fa89..673e42666 100644 --- a/openpower/sv/rfc/ls013.mdwn +++ b/openpower/sv/rfc/ls013.mdwn @@ -61,12 +61,13 @@ TODO **Notes and Observations**: -1. minimum/maximum instructions are needed for vector reductions, where the - SVP64 tree reduction needs a single instruction to work properly. +1. SVP64 REMAP Parallel Reduction needs a single Scalar instruction to + work with, for best effectiveness. With no SFFS minimum/maximum instructions + Simple-V min/max Parallel Reduction is severely compromised. 2. if you implement any of the FP min/max modes, the rest are not much more - hardware. + hardware. 3. SVP64/VSX may have different meaning from SVP64/SFFS, - so it is *really* crucial to have SVP64/SFFS ops even if "equivalent" to VSX. + so it is *really* crucial to have SFFS ops even if "equivalent" to VSX. 4. FP min/max are rather complex to implement in software, the most commonly used FP max function `fmax` from glibc compiled for SFFS is 32 (!) instructions. @@ -84,6 +85,8 @@ Add the following entries to: \newpage{} +# Instructions + ## `FMM` -- Floating Min/Max Mode -- 2.30.2