From d30ab8e0b79a37150f0bbcc8b0d7c390ee47f042 Mon Sep 17 00:00:00 2001 From: Alan Lawrence Date: Tue, 15 Sep 2015 11:39:12 +0000 Subject: [PATCH] [AArch64 array_mode 1/8] Rename vec_store_lanes_lane to aarch64_vec_store_lanes_lane * config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane): Rename to... (aarch64_vec_store_lanesoi_lane): ...this. (vec_store_lanesci_lane): Rename to... (aarch64_vec_store_lanesci_lane): ...this. (vec_store_lanesxi_lane): Rename to... (aarch64_vec_store_lanesxi_lane): ...this. (aarch64_st2_lane, aarch64_st3_lane, aarch64_st4_lane): Follow renaming. From-SVN: r227781 --- gcc/ChangeLog | 15 +++++++++++++++ gcc/config/aarch64/aarch64-simd.md | 18 ++++++++++++------ 2 files changed, 27 insertions(+), 6 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index be8089daa85..95e2d320947 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2015-09-15 Alan Lawrence + + * config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane): Rename + to... + (aarch64_vec_store_lanesoi_lane): ...this. + + (vec_store_lanesci_lane): Rename to... + (aarch64_vec_store_lanesci_lane): ...this. + + (vec_store_lanesxi_lane): Rename to... + (aarch64_vec_store_lanesxi_lane): ...this. + + (aarch64_st2_lane, aarch64_st3_lane, + aarch64_st4_lane): Follow renaming. + 2015-09-15 Andreas Krebbel * config/s390/s390.c (s390_const_operand_ok): Add missing diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index a4eaecae2a0..67cb4c9bffd 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3981,7 +3981,7 @@ ) ;; RTL uses GCC vector extension indices, so flip only for assembly. -(define_insn "vec_store_lanesoi_lane" +(define_insn "aarch64_vec_store_lanesoi_lane" [(set (match_operand: 0 "aarch64_simd_struct_operand" "=Utv") (unspec: [(match_operand:OI 1 "register_operand" "w") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) @@ -4079,7 +4079,7 @@ ) ;; RTL uses GCC vector extension indices, so flip only for assembly. -(define_insn "vec_store_lanesci_lane" +(define_insn "aarch64_vec_store_lanesci_lane" [(set (match_operand: 0 "aarch64_simd_struct_operand" "=Utv") (unspec: [(match_operand:CI 1 "register_operand" "w") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) @@ -4177,7 +4177,7 @@ ) ;; RTL uses GCC vector extension indices, so flip only for assembly. -(define_insn "vec_store_lanesxi_lane" +(define_insn "aarch64_vec_store_lanesxi_lane" [(set (match_operand: 0 "aarch64_simd_struct_operand" "=Utv") (unspec: [(match_operand:XI 1 "register_operand" "w") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) @@ -4886,7 +4886,9 @@ machine_mode mode = mode; rtx mem = gen_rtx_MEM (mode, operands[0]); - emit_insn (gen_vec_store_lanesoi_lane (mem, operands[1], operands[2])); + emit_insn (gen_aarch64_vec_store_lanesoi_lane (mem, + operands[1], + operands[2])); DONE; }) @@ -4900,7 +4902,9 @@ machine_mode mode = mode; rtx mem = gen_rtx_MEM (mode, operands[0]); - emit_insn (gen_vec_store_lanesci_lane (mem, operands[1], operands[2])); + emit_insn (gen_aarch64_vec_store_lanesci_lane (mem, + operands[1], + operands[2])); DONE; }) @@ -4914,7 +4918,9 @@ machine_mode mode = mode; rtx mem = gen_rtx_MEM (mode, operands[0]); - emit_insn (gen_vec_store_lanesxi_lane (mem, operands[1], operands[2])); + emit_insn (gen_aarch64_vec_store_lanesxi_lane (mem, + operands[1], + operands[2])); DONE; }) -- 2.30.2