From d3385ccf2ec935f1c0c382e130467824c628b747 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 20:17:12 +0100 Subject: [PATCH] add both logical and ALU test core --- src/soc/simple/test/test_core.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index da844e34..22bd3bc1 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -14,8 +14,8 @@ from soc.simple.core import NonProductionCore from soc.experiment.compalu_multi import find_ok # hack # test with ALU data and Logical data -from soc.fu.alu.test.test_pipe_caller import TestCase, ALUTestCase, test_data -#from soc.fu.logical.test.test_pipe_caller import LogicalTestCase, test_data +from soc.fu.alu.test.test_pipe_caller import TestCase, ALUTestCase +from soc.fu.logical.test.test_pipe_caller import LogicalTestCase def set_cu_input(cu, idx, data): @@ -218,7 +218,8 @@ class TestRunner(FHDLTestCase): if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() - suite.addTest(TestRunner(test_data)) + suite.addTest(TestRunner(LogicalTestCase.test_data)) + suite.addTest(TestRunner(ALUTestCase.test_data)) runner = unittest.TextTestRunner() runner.run(suite) -- 2.30.2