From d3606ee3ea6a8a30844f997aac61b4a1ecd30242 Mon Sep 17 00:00:00 2001 From: Jocelyn Mayer Date: Thu, 16 Jun 2016 18:09:30 +0200 Subject: [PATCH] driver-i386.c (host_detect_local_cpu): Set PROCESSOR_K8 for signature_CENTAUR_ebx with has_longmode. * config/i386/driver-i386.c (host_detect_local_cpu): Set PROCESSOR_K8 for signature_CENTAUR_ebx with has_longmode. : Pass nano-3000, nano, eden-x2 or k8 for signature_CENTAUR_ebx. * config/i386/i386.c (ix86_option_override_internal): Add definitions for VIA c7, samuel-2, nehemiah, esther, eden-x2, eden-x4, nano, nano-1000, nano-2000, nano-3000, nano-x2 and nano-x4. * doc/invoke.texi: Document new VIA -march entries. From-SVN: r237534 --- gcc/ChangeLog | 11 +++++++ gcc/config/i386/driver-i386.c | 29 ++++++++++++++-- gcc/config/i386/i386.c | 34 +++++++++++++++++-- gcc/doc/invoke.texi | 62 ++++++++++++++++++++++++++++++++--- 4 files changed, 127 insertions(+), 9 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4d6fdf65d6c..5215b801a6b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2016-06-16 Jocelyn Mayer + + * config/i386/driver-i386.c (host_detect_local_cpu): Set + PROCESSOR_K8 for signature_CENTAUR_ebx with has_longmode. + : Pass nano-3000, nano, eden-x2 or k8 for + signature_CENTAUR_ebx. + * config/i386/i386.c (ix86_option_override_internal): Add + definitions for VIA c7, samuel-2, nehemiah, esther, eden-x2, eden-x4, + nano, nano-1000, nano-2000, nano-3000, nano-x2 and nano-x4. + * doc/invoke.texi: Document new VIA -march entries. + 2016-06-16 Martin Liska * predict.def: Add fortran loop preheader predictor. diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index a9d5135f678..9f44ee86391 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -651,7 +651,9 @@ const char *host_detect_local_cpu (int argc, const char **argv) break; case 6: - if (model > 9 || has_longmode) + if (has_longmode) + processor = PROCESSOR_K8; + else if (model > 9) /* Use the default detection procedure. */ ; else if (model == 9) @@ -869,9 +871,30 @@ const char *host_detect_local_cpu (int argc, const char **argv) cpu = "athlon"; break; case PROCESSOR_K8: - if (arch && has_sse3) - cpu = "k8-sse3"; + if (arch) + { + if (vendor == signature_CENTAUR_ebx) + { + if (has_sse4_1) + /* Nano 3000 | Nano dual / quad core | Eden X4 */ + cpu = "nano-3000"; + else if (has_ssse3) + /* Nano 1000 | Nano 2000 */ + cpu = "nano"; + else if (has_sse3) + /* Eden X2 */ + cpu = "eden-x2"; + else + /* Default to k8 */ + cpu = "k8"; + } + else if (has_sse3) + cpu = "k8-sse3"; + else + cpu = "k8"; + } else + /* For -mtune, we default to -mtune=k8 */ cpu = "k8"; break; case PROCESSOR_AMDFAM10: diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index c5e5e1238a5..56a5b9c3296 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -4783,8 +4783,15 @@ ix86_option_override_internal (bool main_args_p, {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX}, {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW}, {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW}, + {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW}, {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_FXSR}, + {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, + PTA_MMX | PTA_SSE | PTA_FXSR}, + {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, + PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR}, + {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, + PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR}, {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0}, {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0}, {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR}, @@ -4843,6 +4850,29 @@ ix86_option_override_internal (bool main_args_p, PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_PRFCHW | PTA_FXSR}, {"x86-64", PROCESSOR_K8, CPU_K8, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR}, + {"eden-x2", PROCESSOR_K8, CPU_K8, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR}, + {"nano", PROCESSOR_K8, CPU_K8, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_FXSR}, + {"nano-1000", PROCESSOR_K8, CPU_K8, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_FXSR}, + {"nano-2000", PROCESSOR_K8, CPU_K8, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_FXSR}, + {"nano-3000", PROCESSOR_K8, CPU_K8, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR}, + {"nano-x2", PROCESSOR_K8, CPU_K8, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR}, + {"eden-x4", PROCESSOR_K8, CPU_K8, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR}, + {"nano-x4", PROCESSOR_K8, CPU_K8, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR}, {"k8", PROCESSOR_K8, CPU_K8, PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR}, @@ -4888,7 +4918,7 @@ ix86_option_override_internal (bool main_args_p, | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE}, - {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4, + {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 @@ -4905,7 +4935,7 @@ ix86_option_override_internal (bool main_args_p, | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES | PTA_SHA | PTA_LZCNT | PTA_POPCNT}, - {"btver1", PROCESSOR_BTVER1, CPU_GENERIC, + {"btver1", PROCESSOR_BTVER1, CPU_GENERIC, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE}, diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 78734786829..741ccce5726 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -23357,13 +23357,67 @@ IDT WinChip 2 CPU, dealt in same way as i486 with additional MMX and 3DNow!@: instruction set support. @item c3 -VIA C3 CPU with MMX and 3DNow!@: instruction set support. (No scheduling is -implemented for this chip.) +VIA C3 CPU with MMX and 3DNow!@: instruction set support. +(No scheduling is implemented for this chip.) @item c3-2 VIA C3-2 (Nehemiah/C5XL) CPU with MMX and SSE instruction set support. -(No scheduling is -implemented for this chip.) +(No scheduling is implemented for this chip.) + +@item c7 +VIA C7 (Esther) CPU with MMX, SSE, SSE2 and SSE3 instruction set support. +(No scheduling is implemented for this chip.) + +@item samuel-2 +VIA Eden Samuel 2 CPU with MMX and 3DNow!@: instruction set support. +(No scheduling is implemented for this chip.) + +@item nehemiah +VIA Eden Nehemiah CPU with MMX and SSE instruction set support. +(No scheduling is implemented for this chip.) + +@item esther +VIA Eden Esther CPU with MMX, SSE, SSE2 and SSE3 instruction set support. +(No scheduling is implemented for this chip.) + +@item eden-x2 +VIA Eden X2 CPU with x86-64, MMX, SSE, SSE2 and SSE3 instruction set support. +(No scheduling is implemented for this chip.) + +@item eden-x4 +VIA Eden X4 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, +AVX and AVX2 instruction set support. +(No scheduling is implemented for this chip.) + +@item nano +Generic VIA Nano CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3 +instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-1000 +VIA Nano 1xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3 +instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-2000 +VIA Nano 2xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3 +instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-3000 +VIA Nano 3xxx CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 +instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-x2 +VIA Nano Dual Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 +instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-x4 +VIA Nano Quad Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 +instruction set support. +(No scheduling is implemented for this chip.) @item geode AMD Geode embedded processor with MMX and 3DNow!@: instruction set support. -- 2.30.2