From d368a89bbfb41c5581bc9d81916b73a47a10560b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 20 Dec 2014 01:26:02 +0100 Subject: [PATCH] fix ack in idle in some fsm (implementation behaviour different from simulation) --- lib/sata/command/__init__.py | 1 + lib/sata/transport/__init__.py | 3 +++ 2 files changed, 4 insertions(+) diff --git a/lib/sata/command/__init__.py b/lib/sata/command/__init__.py index 5d7b6348..4dae7d59 100644 --- a/lib/sata/command/__init__.py +++ b/lib/sata/command/__init__.py @@ -33,6 +33,7 @@ class SATACommandTX(Module): self.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", + sink.ack.eq(0), If(sink.stb & sink.sop, If(sink.write, NextState("SEND_WRITE_DMA_CMD") diff --git a/lib/sata/transport/__init__.py b/lib/sata/transport/__init__.py index a4fd4bd7..d5148424 100644 --- a/lib/sata/transport/__init__.py +++ b/lib/sata/transport/__init__.py @@ -41,6 +41,7 @@ class SATATransportTX(Module): self.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", + sink.ack.eq(0), counter.reset.eq(1), If(sink.stb & sink.sop, If(test_type("REG_H2D"), @@ -64,6 +65,7 @@ class SATATransportTX(Module): ) ) fsm.act("SEND_DATA_CMD", + sink.ack.eq(0), _encode_cmd(sink, fis_data_layout, encoded_cmd), cmd_len.eq(fis_data_cmd_len-1), cmd_with_data.eq(1), @@ -134,6 +136,7 @@ class SATATransportRX(Module): data_sop = Signal() fsm.act("IDLE", + link.source.ack.eq(0), counter.reset.eq(1), If(link.source.stb & link.source.sop, If(test_type("REG_D2H"), -- 2.30.2