From d38df68d26f1644539e5116e6b6c360e1c389cc9 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 16 Jul 2019 17:53:08 +0100
Subject: [PATCH] xilinx: Add correct signed behaviour to DSP48E1 model

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/xilinx/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 99120452c..ea5a3b788 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -506,6 +506,6 @@ module DSP48E1 (
         if (PCIN != 48'b0)          $fatal(1, "Unsupported PCIN value");
         if (CARRYIN != 1'b0)        $fatal(1, "Unsupported CARRYIN value");
 `endif
-        P[42:0] <= A[24:0] * B;
+        P[42:0] <= $signed(A[24:0]) * $signed(B);
     end
 endmodule
-- 
2.30.2