From d3959070aa46635734a9f3ad68ce4d95d1445673 Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Fri, 15 Jan 2021 17:55:57 +0000 Subject: [PATCH] [PATCH] aarch64: Implement vmlsl[_high]* intrinsics using builtins This patch reimplements some more intrinsics using RTL builtins in the straightforward way. Thankfully most of the RTL infrastructure is already in place for it. gcc/ * config/aarch64/aarch64-simd.md (*aarch64_mlsl_hi): Rename to... (aarch64_mlsl_hi): ... This. (aarch64_mlsl_hi): Define. (*aarch64_mlslmlsl. */ BUILTIN_VQN (UNOP, xtn, 0, NONE) + /* Implemented by aarch64_mlsl. */ + BUILTIN_VD_BHSI (TERNOP, smlsl, 0, NONE) + BUILTIN_VD_BHSI (TERNOPU, umlsl, 0, NONE) + + /* Implemented by aarch64_mlsl_hi. */ + BUILTIN_VQW (TERNOP, smlsl_hi, 0, NONE) + BUILTIN_VQW (TERNOPU, umlsl_hi, 0, NONE) + BUILTIN_VSQN_HSDI (UNOPUS, sqmovun, 0, ALL) /* Implemented by aarch64_qmovn. */ BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0, ALL) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 4b869ded918..eabc915c681 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1755,7 +1755,7 @@ [(set_attr "type" "neon_mla__long")] ) -(define_insn "*aarch64_mlsl_hi" +(define_insn "aarch64_mlsl_hi_insn" [(set (match_operand: 0 "register_operand" "=w") (minus: (match_operand: 1 "register_operand" "0") @@ -1771,6 +1771,20 @@ [(set_attr "type" "neon_mla__long")] ) +(define_expand "aarch64_mlsl_hi" + [(match_operand: 0 "register_operand") + (match_operand: 1 "register_operand") + (ANY_EXTEND:(match_operand:VQW 2 "register_operand")) + (match_operand:VQW 3 "register_operand")] + "TARGET_SIMD" +{ + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); + emit_insn (gen_aarch64_mlsl_hi_insn (operands[0], operands[1], + operands[2], p, operands[3])); + DONE; +} +) + (define_insn "*aarch64_mlal" [(set (match_operand: 0 "register_operand" "=w") (plus: @@ -1785,7 +1799,7 @@ [(set_attr "type" "neon_mla__long")] ) -(define_insn "*aarch64_mlsl" +(define_insn "aarch64_mlsl" [(set (match_operand: 0 "register_operand" "=w") (minus: (match_operand: 1 "register_operand" "0") diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 46331ae6f95..f7efee61de4 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -8200,72 +8200,42 @@ __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_high_s8 (int16x8_t __a, int8x16_t __b, int8x16_t __c) { - int16x8_t __result; - __asm__ ("smlsl2 %0.8h,%2.16b,%3.16b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlsl_hiv16qi (__a, __b, __c); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c) { - int32x4_t __result; - __asm__ ("smlsl2 %0.4s,%2.8h,%3.8h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlsl_hiv8hi (__a, __b, __c); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c) { - int64x2_t __result; - __asm__ ("smlsl2 %0.2d,%2.4s,%3.4s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlsl_hiv4si (__a, __b, __c); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_high_u8 (uint16x8_t __a, uint8x16_t __b, uint8x16_t __c) { - uint16x8_t __result; - __asm__ ("umlsl2 %0.8h,%2.16b,%3.16b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlsl_hiv16qi_uuuu (__a, __b, __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_high_u16 (uint32x4_t __a, uint16x8_t __b, uint16x8_t __c) { - uint32x4_t __result; - __asm__ ("umlsl2 %0.4s,%2.8h,%3.8h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlsl_hiv8hi_uuuu (__a, __b, __c); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_high_u32 (uint64x2_t __a, uint32x4_t __b, uint32x4_t __c) { - uint64x2_t __result; - __asm__ ("umlsl2 %0.2d,%2.4s,%3.4s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlsl_hiv4si_uuuu (__a, __b, __c); } #define vmlsl_lane_s16(a, b, c, d) \ @@ -8432,72 +8402,42 @@ __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_s8 (int16x8_t __a, int8x8_t __b, int8x8_t __c) { - int16x8_t __result; - __asm__ ("smlsl %0.8h, %2.8b, %3.8b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlslv8qi (__a, __b, __c); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c) { - int32x4_t __result; - __asm__ ("smlsl %0.4s, %2.4h, %3.4h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlslv4hi (__a, __b, __c); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c) { - int64x2_t __result; - __asm__ ("smlsl %0.2d, %2.2s, %3.2s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlslv2si (__a, __b, __c); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_u8 (uint16x8_t __a, uint8x8_t __b, uint8x8_t __c) { - uint16x8_t __result; - __asm__ ("umlsl %0.8h, %2.8b, %3.8b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlslv8qi_uuuu (__a, __b, __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c) { - uint32x4_t __result; - __asm__ ("umlsl %0.4s, %2.4h, %3.4h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlslv4hi_uuuu (__a, __b, __c); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c) { - uint64x2_t __result; - __asm__ ("umlsl %0.2d, %2.2s, %3.2s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlslv2si_uuuu (__a, __b, __c); } __extension__ extern __inline float32x4_t -- 2.30.2