From d3aa01eed9972bf1e20e3a6888b27f648a4730da Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Thu, 5 Jan 2012 11:00:45 -0600 Subject: [PATCH] MESI Coherence Protocol: Fix L2 miss statistics This patch removes calls to uu_ProfileMiss from transitions where the request is satisfied by the L2 cache controller. --HG-- extra : rebase_source : e59fe7c6cd5795c0019cf178dd3b062d73cc2ff5 --- src/mem/protocol/MESI_CMP_directory-L2cache.sm | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm index 2d8ae4ca8..16c5bc5a1 100644 --- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm @@ -913,7 +913,6 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") transition(SS, {L1_GETS, L1_GET_INSTR}) { ds_sendSharedDataToRequestor; nn_addSharer; - uu_profileMiss; set_setMRU; jj_popL1RequestQueue; } @@ -923,7 +922,6 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") d_sendDataToRequestor; // fw_sendFwdInvToSharers; fwm_sendFwdInvToSharersMinusRequestor; - uu_profileMiss; set_setMRU; jj_popL1RequestQueue; } @@ -931,7 +929,6 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") transition(SS, L1_UPGRADE, SS_MB) { fwm_sendFwdInvToSharersMinusRequestor; ts_sendInvAckToUpgrader; - uu_profileMiss; set_setMRU; jj_popL1RequestQueue; } @@ -951,7 +948,6 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") transition(M, L1_GETX, MT_MB) { d_sendDataToRequestor; - uu_profileMiss; set_setMRU; jj_popL1RequestQueue; } @@ -959,14 +955,12 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") transition(M, L1_GET_INSTR, SS) { d_sendDataToRequestor; nn_addSharer; - uu_profileMiss; set_setMRU; jj_popL1RequestQueue; } transition(M, L1_GETS, MT_MB) { dd_sendExclusiveDataToRequestor; - uu_profileMiss; set_setMRU; jj_popL1RequestQueue; } -- 2.30.2