From d3ae55937830853349bcc80298714167839c42f2 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Mon, 15 Jun 2020 14:24:00 -0700 Subject: [PATCH] freedreno/ir3: add ir3_finalize_nir() The next step is to hook this into pscreen->finalize_nir() so it can come before the state tracker's shader-caching. Unfortunately we still need to do lower_io after mesa/st, so that is split out into a post-finalize pass. Signed-off-by: Rob Clark Part-of: --- src/freedreno/ir3/ir3_nir.c | 51 ++++++++++++++++--- src/freedreno/ir3/ir3_nir.h | 3 +- src/freedreno/ir3/ir3_shader.c | 29 ++--------- .../drivers/freedreno/ir3/ir3_cmdline.c | 2 +- 4 files changed, 49 insertions(+), 36 deletions(-) diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c index bf2db6b6c9c..5c15f5b8dfc 100644 --- a/src/freedreno/ir3/ir3_nir.c +++ b/src/freedreno/ir3/ir3_nir.c @@ -215,14 +215,14 @@ should_split_wrmask(const nir_instr *instr, const void *data) } void -ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s) +ir3_finalize_nir(struct ir3_compiler *compiler, nir_shader *s) { struct nir_lower_tex_options tex_options = { .lower_rect = 0, .lower_tg4_offsets = true, }; - if (shader->compiler->gpu_id >= 400) { + if (compiler->gpu_id >= 400) { /* a4xx seems to have *no* sam.p */ tex_options.lower_txp = ~0; /* lower all txp */ } else { @@ -236,17 +236,19 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s) debug_printf("----------------------\n"); } - OPT_V(s, nir_lower_regs_to_ssa); - OPT_V(s, nir_lower_wrmasks, should_split_wrmask, s); + if (s->info.stage == MESA_SHADER_GEOMETRY) + NIR_PASS_V(s, ir3_nir_lower_gs); - OPT_V(s, ir3_nir_apply_trig_workarounds); + NIR_PASS_V(s, nir_lower_io_arrays_to_elements_no_indirects, false); - if (shader->type == MESA_SHADER_FRAGMENT) - OPT_V(s, nir_lower_fb_read); + NIR_PASS_V(s, nir_lower_amul, ir3_glsl_type_size); + + OPT_V(s, nir_lower_regs_to_ssa); + OPT_V(s, nir_lower_wrmasks, should_split_wrmask, s); OPT_V(s, nir_lower_tex, &tex_options); OPT_V(s, nir_lower_load_const_to_scalar); - if (shader->compiler->gpu_id < 500) + if (compiler->gpu_id < 500) OPT_V(s, ir3_nir_lower_tg4_to_tex); ir3_optimize_loop(s); @@ -270,6 +272,39 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s) nir_sweep(s); } +/** + * Late passes that need to be done after pscreen->finalize_nir() + */ +void +ir3_nir_post_finalize(struct ir3_compiler *compiler, nir_shader *s) +{ + NIR_PASS_V(s, nir_lower_io, nir_var_all, ir3_glsl_type_size, + (nir_lower_io_options)0); + + if (s->info.stage == MESA_SHADER_FRAGMENT) { + /* NOTE: lower load_barycentric_at_sample first, since it + * produces load_barycentric_at_offset: + */ + NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_sample); + NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_offset); + NIR_PASS_V(s, ir3_nir_move_varying_inputs); + NIR_PASS_V(s, nir_lower_fb_read); + } + + if (compiler->gpu_id >= 600 && + s->info.stage == MESA_SHADER_FRAGMENT && + !(ir3_shader_debug & IR3_DBG_NOFP16)) { + NIR_PASS_V(s, nir_lower_mediump_outputs); + } + + /* we cannot ensure that ir3_finalize_nir() is only called once, so + * we also need to do trig workarounds here: + */ + OPT_V(s, ir3_nir_apply_trig_workarounds); + + ir3_optimize_loop(s); +} + void ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s) { diff --git a/src/freedreno/ir3/ir3_nir.h b/src/freedreno/ir3/ir3_nir.h index b84525bd69f..8bc6d342fe0 100644 --- a/src/freedreno/ir3/ir3_nir.h +++ b/src/freedreno/ir3/ir3_nir.h @@ -52,7 +52,8 @@ void ir3_nir_lower_tess_eval(nir_shader *shader, unsigned topology); void ir3_nir_lower_gs(nir_shader *shader); const nir_shader_compiler_options * ir3_get_compiler_options(struct ir3_compiler *compiler); -void ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s); +void ir3_finalize_nir(struct ir3_compiler *compiler, nir_shader *s); +void ir3_nir_post_finalize(struct ir3_compiler *compiler, nir_shader *s); void ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s); void ir3_setup_const_state(nir_shader *nir, struct ir3_shader_variant *v, diff --git a/src/freedreno/ir3/ir3_shader.c b/src/freedreno/ir3/ir3_shader.c index 37e1f8bfb2c..afdce9d0f82 100644 --- a/src/freedreno/ir3/ir3_shader.c +++ b/src/freedreno/ir3/ir3_shader.c @@ -409,35 +409,12 @@ ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir, memcpy(&shader->stream_output, stream_output, sizeof(shader->stream_output)); shader->num_reserved_user_consts = reserved_user_consts; - if (nir->info.stage == MESA_SHADER_GEOMETRY) - NIR_PASS_V(nir, ir3_nir_lower_gs); + ir3_nir_post_finalize(compiler, nir); - NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size, - (nir_lower_io_options)0); - - if (compiler->gpu_id >= 600 && - nir->info.stage == MESA_SHADER_FRAGMENT && - !(ir3_shader_debug & IR3_DBG_NOFP16)) - NIR_PASS_V(nir, nir_lower_mediump_outputs); - - if (nir->info.stage == MESA_SHADER_FRAGMENT) { - /* NOTE: lower load_barycentric_at_sample first, since it - * produces load_barycentric_at_offset: - */ - NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_sample); - NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_offset); - - NIR_PASS_V(nir, ir3_nir_move_varying_inputs); - } - - NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false); - - NIR_PASS_V(nir, nir_lower_amul, ir3_glsl_type_size); - - /* do first pass optimization, ignoring the key: */ - ir3_optimize_nir(shader, nir); + ir3_finalize_nir(compiler, nir); shader->nir = nir; + if (ir3_shader_debug & IR3_DBG_DISASM) { printf("dump nir%d: type=%d", shader->id, shader->type); nir_print_shader(shader->nir, stdout); diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c index cd9950436c5..0498c5828ad 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c @@ -491,7 +491,7 @@ int main(int argc, char **argv) s.compiler = compiler; s.nir = nir; - ir3_optimize_nir(&s, nir); + ir3_finalize_nir(compiler, nir); v.key = key; v.shader = &s; -- 2.30.2