From d3bb6f5635d75a31cbc3fbc15fed96d264ebc620 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 27 Oct 2023 10:56:58 +0100 Subject: [PATCH] remove immediate-versions of instructions for shifting as there is no point shifting an immediate --- openpower/isa/pifixedloadshift.mdwn | 103 ------------------------- openpower/isa/pifixedstoreshift.mdwn | 108 --------------------------- openpower/isa/pifploadshift.mdwn | 56 -------------- openpower/isa/pifpstoreshift.mdwn | 55 -------------- 4 files changed, 322 deletions(-) diff --git a/openpower/isa/pifixedloadshift.mdwn b/openpower/isa/pifixedloadshift.mdwn index 0418b1cd..98d7edd6 100644 --- a/openpower/isa/pifixedloadshift.mdwn +++ b/openpower/isa/pifixedloadshift.mdwn @@ -8,32 +8,6 @@ -# Load Byte and Zero with Post-Update - -D-Form - -* lbzup RT,D(RA) - -Pseudo-code: - - EA <- (RA) - RT <- ([0] * (XLEN-8)) || MEM(EA, 1) - RA <- (RA) + EXTS(D) - -Description: - - Let the effective address (EA) be register RA. - The byte in storage addressed by EA is loaded into RT[56:63]. - RT[0:55] are set to 0. - - The sum (RA) + D is placed into register RA. - - If RA=0 or RA=RT, the instruction form is invalid. - -Special Registers Altered: - - None - # Load Byte and Zero with Post-Update Indexed X-Form @@ -60,32 +34,6 @@ Special Registers Altered: None -# Load Halfword and Zero with Post-Update - -D-Form - -* lhzup RT,D(RA) - -Pseudo-code: - - EA <- (RA) - RT <- ([0] * (XLEN-16)) || MEM(EA, 2) - RA <- (RA) + EXTS(D) - -Description: - - Let the effective address (EA) be register RA. - The halfword in storage addressed by EA is loaded into RT[48:63]. - RT[0:47] are set to 0. - - The sum (RA) + D is placed into register RA. - - If RA=0 or RA=RT, the instruction form is invalid. - -Special Registers Altered: - - None - # Load Halfword and Zero with Post-Update Indexed X-Form @@ -164,32 +112,6 @@ Special Registers Altered: None -# Load Word and Zero with Post-Update - -D-Form - -* lwzup RT,D(RA) - -Pseudo-code: - - EA <- (RA) - RT <- [0]*32 || MEM(EA, 4) - RA <- (RA) + EXTS(D) - -Description: - - Let the effective address (EA) be the register RA. - The halfword in storage addressed by EA is loaded into RT[48:63]. - RT[0:47] are filled with a copy of bit 0 of the loaded halfword. - - The sum (RA) + D is placed into register RA. - - If RA=0 or RA=RT, the instruction form is invalid. - -Special Registers Altered: - - None - # Load Word and Zero with Post-Update Indexed X-Form @@ -244,31 +166,6 @@ Special Registers Altered: # Load Doubleword with Post-Update Indexed -DS-Form - -* ldup RT,DS(RA) - -Pseudo-code: - - EA <- (RA) - RT <- MEM(EA, 8) - RA <- (RA) + EXTS(DS || 0b00) - -Description: - - Let the effective address (EA) be the register RA. - The doubleword in storage addressed by EA is loaded into RT. - - The sum (RA)+ (DS||0b00) is placed into register RA. - - If RA=0 or RA=RT, the instruction form is invalid. - -Special Registers Altered: - - None - -# Load Doubleword with Post-Update Indexed - X-Form * ldupx RT,RA,RB diff --git a/openpower/isa/pifixedstoreshift.mdwn b/openpower/isa/pifixedstoreshift.mdwn index dfccc495..8dbcb445 100644 --- a/openpower/isa/pifixedstoreshift.mdwn +++ b/openpower/isa/pifixedstoreshift.mdwn @@ -3,34 +3,6 @@ -# Store Byte with Post-Update - -D-Form - -* stbup RS,D(RA) - -Pseudo-code: - - EA <- (RA) + EXTS(D) - ea <- (RA) - MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1] - RA <- EA - -Description: - - Let the effective address (EA) be the sum (RA)+ D. - - (RS)[56:63] are stored into the byte in storage addressed - by RA. - - EA is placed into register RA. - - If RA=0, the instruction form is invalid. - -Special Registers Altered: - - None - # Store Byte with Post-Update Indexed X-Form @@ -59,30 +31,6 @@ Special Registers Altered: None -# Store Halfword with Post-Update - -D-Form - -* sthup RS,D(RA) - -Pseudo-code: - - EA <- (RA) + EXTS(D) - ea <- (RA) - MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1] - RA <- EA - -Description: - - Let the effective address (EA) be the sum (RA|0)+ D. - - (RS)[48:63] are stored into the halfword in storage - addressed by EA. - -Special Registers Altered: - - None - # Store Halfword with Post-Update Indexed X-Form @@ -111,34 +59,6 @@ Special Registers Altered: None -# Store Word with Post-Update - -D-Form - -* stwup RS,D(RA) - -Pseudo-code: - - EA <- (RA) + EXTS(D) - ea <- (RA) - MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1] - RA <- EA - -Description: - - Let the effective address (EA) be the sum (RA)+ D. - - (RS)[32:63] are stored into the word in storage addressed - by EA. - - EA is placed into register RA. - - If RA=0, the instruction form is invalid. - -Special Registers Altered: - - None - # Store Word with Post-Update Indexed X-Form @@ -167,34 +87,6 @@ Special Registers Altered: None -# Store Doubleword with Post-Update - -DS-Form - -* stdup RS,DS(RA) - -Pseudo-code: - - EA <- (RA) + EXTS(DS || 0b00) - ea <- (RA) - MEM(ea, 8) <- (RS) - RA <- EA - -Description: - - Let the effective address (EA) be the sum. - - (RA)+ (DS||0b00). (RS) is stored into the doubleword in - storage addressed by RA. - - EA is placed into register RA. - - If RA=0, the instruction form is invalid. - -Special Registers Altered: - - None - # Store Doubleword with Post-Update Indexed X-Form diff --git a/openpower/isa/pifploadshift.mdwn b/openpower/isa/pifploadshift.mdwn index d9de3315..281ec280 100644 --- a/openpower/isa/pifploadshift.mdwn +++ b/openpower/isa/pifploadshift.mdwn @@ -2,35 +2,6 @@ -# Load Floating-Point Single with Post-Update - -D-Form - -* lfsup FRT,D(RA) - -Pseudo-code: - - EA <- (RA) + EXTS(D) - FRT <- DOUBLE(MEM(RA, 4)) - RA <- EA - -Description: - - Let the effective address (EA) be the sum (RA)+D. - - The word in storage addressed by EA is interpreted as - a floating-point single-precision operand. This word is - converted to floating-point double format (see - page 138) and placed into register FRT. - - EA is placed into register RA. - - If RA=0, the instruction form is invalid. - -Special Registers Altered: - - None - # Load Floating-Point Single with Post-Update Indexed X-Form @@ -60,33 +31,6 @@ Special Registers Altered: None -# Load Floating-Point Double with Post-Update - -D-Form - -* lfdup FRT,D(RA) - -Pseudo-code: - - EA <- (RA) + EXTS(D) - FRT <- MEM(RA, 8) - RA <- EA - -Description: - - Let the effective address (EA) be the sum (RA)+D. - - The doubleword in storage addressed by EA is loaded - into register FRT. - - EA is placed into register RA. - - If RA=0, the instruction form is invalid. - -Special Registers Altered: - - None - # Load Floating-Point Double with Post-Update Indexed X-Form diff --git a/openpower/isa/pifpstoreshift.mdwn b/openpower/isa/pifpstoreshift.mdwn index 46dd74fa..b16be32a 100644 --- a/openpower/isa/pifpstoreshift.mdwn +++ b/openpower/isa/pifpstoreshift.mdwn @@ -2,34 +2,6 @@ -# Store Floating-Point Single with Update - -D-Form - -* stfsu FRS,D(RA) - -Pseudo-code: - - EA <- (RA) + EXTS(D) - MEM(RA, 4)<- SINGLE( (FRS) ) - RA <- EA - -Description: - - Let the effective address (EA) be the sum (RA) +D. - - The contents of register FRS are converted to single - format (see page 142) and stored into the word in stor- - age addressed by RA. - - EA is placed into register RA. - - If RA=0, the instruction form is invalid. - -Special Registers Altered: - - None - # Store Floating-Point Single with Update Indexed X-Form @@ -58,33 +30,6 @@ Special Registers Altered: None -# Store Floating-Point Double with Update - -D-Form - -* stfdu FRS,D(RA) - -Pseudo-code: - - EA <- (RA) + EXTS(D) - MEM(RA, 8)<- (FRS) - RA <- EA - -Description: - - Let the effective address (EA) be the sum (RA)+D. - - The contents of register FRS are stored into the dou- - bleword in storage addressed by RA. - - EA is placed into register RA. - - If RA=0, the instruction form is invalid. - -Special Registers Altered: - - None - # Store Floating-Point Double with Update Indexed X-Form -- 2.30.2