From d3c7a0ddc169877e8daf38a347091c366e85624b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 9 Dec 2023 06:47:26 +0000 Subject: [PATCH] reenable tests --- .../decoder/isa/test_caller_svp64_dd_ffirst.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py b/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py index 6e4f54b4..c371830c 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py +++ b/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py @@ -114,7 +114,7 @@ class DDFFirstTestCase(FHDLTestCase): self.assertEqual(sim.svstate.srcstep, 0) self.assertEqual(sim.svstate.dststep, 0) - def tst_1(self): + def test_1(self): lst = SVP64Asm(["sv.cmpi/ff=lt 0, 1, *10, 5" ]) lst = list(lst) @@ -173,7 +173,7 @@ class DDFFirstTestCase(FHDLTestCase): self.assertEqual(sim.svstate.srcstep, 0) self.assertEqual(sim.svstate.dststep, 0) - def tst_sv_addi_ffirst_le(self): + def test_sv_addi_ffirst_le(self): lst = SVP64Asm(["sv.subf./ff=le *0,8,*0" ]) lst = list(lst) @@ -230,7 +230,7 @@ class DDFFirstTestCase(FHDLTestCase): self.assertEqual(sim.svstate.srcstep, 0) self.assertEqual(sim.svstate.dststep, 0) - def tst_sv_addi_ffirst(self): + def test_sv_addi_ffirst(self): lst = SVP64Asm(["sv.subf./ff=eq *0,8,*0" ]) lst = list(lst) @@ -282,7 +282,7 @@ class DDFFirstTestCase(FHDLTestCase): self.assertEqual(sim.svstate.srcstep, 0) self.assertEqual(sim.svstate.dststep, 0) - def tst_sv_addi_ffirst_rc1(self): + def test_sv_addi_ffirst_rc1(self): lst = SVP64Asm(["sv.subf/ff=RC1 *0,8,*0" # RC1 auto-sets EQ (and Rc=1) ]) lst = list(lst) @@ -325,7 +325,7 @@ class DDFFirstTestCase(FHDLTestCase): self.assertEqual(sim.svstate.srcstep, 0) self.assertEqual(sim.svstate.dststep, 0) - def tst_sv_addi_ffirst_vli(self): + def test_sv_addi_ffirst_vli(self): """data-dependent fail-first with VLi=1, the test comes *after* write """ lst = SVP64Asm(["sv.subf/ff=RC1/vli *0,8,*0" -- 2.30.2