From d3d2081026437b46fb49884bcdc58df6c7b45ed3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 2 Jul 2018 17:26:54 +0100 Subject: [PATCH] add spec testing.py --- src/spec/testing.py | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 src/spec/testing.py diff --git a/src/spec/testing.py b/src/spec/testing.py new file mode 100644 index 0000000..fc866cb --- /dev/null +++ b/src/spec/testing.py @@ -0,0 +1,32 @@ +from UserDict import UserDict + +class Wire(object): + """ a wire which can be hi, lo or tri-state + """ + def __init__(self, wires, name): + self.wires = wires + self.wires[name] = self + self.name = name + self.val = 'x' + +class TestPin(object): + """ a test pin can be an output, input or in-out + and it stores the state in an associated wire + """ + +class Wires(UserDict): + """ a set of wires + """ + def __init__(self): + UserDict.__init__(self) + +def dummytest(ps, output_dir, output_type): + print ps, output_dir, output_type + print dir(ps) + print ps.fnspec + + # basically we need to replicate the entirety of the + # verilog module's inputs and outputs, so that we can + # set inputs hi/lo and then test expected outputs hi/lo. + # so, set up some wires by going through the interfaces + w = Wires() -- 2.30.2